Models and methods of inter-gate resynthesis at the transistor level for nanoelectronic circuits based on FinFETs

Gavrilov, S. V.; Ryzhova, D.I.; Vasilyev, Nikolay O.

doi:10.1109/eiconrus.2018.8317350

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Cited by 4 publications

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“…Results with and without delay control were obtained. In addition, the algorithm of inter-gate resynthesis has already established itself as efficient and fast in the field of designing blocks and elements on promising FinFET technologies [10].…”

Section: Discussionmentioning

confidence: 99%

Algorithm of Structural Optimization for Digital CMOS Circuits

Гаврилов

Ryzhova

Vasilyev

et al. 2019

MES

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In this article we offer area optimization algorithm for digital CMOS circuits that combine two optimization stages. The first one based on the laws of Boolean algebra and reduces circuit area by optimizing Boolean function. The second approach reduces area by removing isolating gates between adjacent transistors. The concept of transistor orientations is used for this purpose. These approaches are performed in an optimization cycle based on a simulated annealing algorithm.

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Section: Discussionmentioning

confidence: 99%