Algorithm of Structural Optimization for Digital CMOS Circuits

Abstract

In this article we offer area optimization algorithm for digital CMOS circuits that combine two optimization stages. The first one based on the laws of Boolean algebra and reduces circuit area by optimizing Boolean function. The second approach reduces area by removing isolating gates between adjacent transistors. The concept of transistor orientations is used for this purpose. These approaches are performed in an optimization cycle based on a simulated annealing algorithm.