Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

Gerrer, Louis; Ding, Jie; Amoroso, Salvatore; Adamu-Lema, Fikru; Hussin, Razaidi; Reid, D.; Millar, C.; Asenov, A.

doi:10.1016/j.microrel.2014.01.024

Cited by 38 publications

(15 citation statements)

References 24 publications

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“…With the experimentally determined g0, m, n, and η as the inputs, µ_ ΔVthGD and µ_ NGD at any Vgov and t can be calculated by eqs. (1) and (5), respectively. If one uses M devices for each stress time, the number of traps per device can be randomly assigned using the Poisson distribution of an average µ_NGD and the impact of each trap on a device, δVthGD, can be generated from the exponential distribution.…”

Section: A Within-device-fluctuation (Wdf) Of Gdsmentioning

confidence: 99%

“…As the CMOS nodes scale down to nano-meter regime, time-dependent variations induced by negative bias temperature instability (NBTI) has become a big concern for circuit design [1][2][3][4][5]. These nano-scaled devices are dominated by only a handful of defects, which are usually categorized into the recoverable and permanent components [6].…”

Section: Introductionmentioning

confidence: 99%

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NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Gao

Manut

et al. 2017

IEEE Trans. Electron Devices

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Section: A Within-device-fluctuation (Wdf) Of Gdsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Gao

Manut

et al. 2017

IEEE Trans. Electron Devices

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“…Another important reliability issue in miniaturized devices is the so called bias temperature instabilities (BTI) [ 19 , 20 , 21 , 22 , 23 , 24 ]. BTI typically manifest as a drift of the drain-source current over time when constant biases are applied to a transistor, and is studied up electric oxide fields of

.…”

Section: Introductionmentioning

confidence: 99%

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Waltl

2020

Micromachines

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To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed.

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“…In one test device, two active traps (D1 and D2) can be identified during the monitoring step measurement in the pristine state, as is apparent from the two distinct|Id| recovery steps in some of the selected relaxation traces (Figure 4 trapping by the CHH stress [137], as is manifested by the upshift in |Id| eoc after each stress. Simulation study [123] has shown that a trap's |Id| recovery step is dependent on the local inversion charge density, which is reduced after the generation of more positive oxide/interface trapped charges by the CHH stress.…”

Section: Channel Hot-hole Effectmentioning

confidence: 99%

Oxide-defects driven study on reliability and synaptic response characterization of logic devices

Ju¹

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for their technical conversations and knowledge sharing. In particular, I would also like to thank Dr. Lin Ye for being very supportive in many aspects during my doctoral study. Senior Sing Yew, appreciate your patience in helping to proofread the thesis. Your feedback is particularly helpful! Greatest gratitude to their assistance, I can carry out experimental research so smoothly and thoroughly.I would like to owe a vote of thanks to the well-experienced technicians in NTU Semiconductor Characterization Lab, Mr. Seow Yong Hing, Ms. Seet Lye Ping, and Mr. Ng Yong Chiang, for their technical and maintenance support in the prober stations. I also extend my gratefulness and cherish the friendship from Zhiyi, Xinhua, Yuxi, Brain Jia Xu, Fang Qiang, Yuanbo, and all my friends in NTU for their help and lovely companions.In addition, I would like to extend my gratitude to the thesis advisory committee members -Prof. Kim Tae Hyoung and Prof. Tang Xiaohong, for their constructive reviews, sharp proposals, and timely suggestions which have helped me to be more focused on the project direction and enriched my research insight. I am grateful to the Ministry of Education Singapore and Nanyang Technological University for a 4-year generous co-funding research scholarship.Last but not least, I would like to dedicate this dissertation to my familyparticularly my dearest parents Ju Zhoufeng and Liu Yaling. They have always been by my side whenever I need it. Their everlasting love and unconditional care have been constant supports for me to keep moving forward in my life and, I am forever thankful.

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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

Cited by 38 publications

References 24 publications

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

NBTI-Generated Defects in Nanoscaled Devices: Fast Characterization Methodology and Modeling

Reliability of Miniaturized Transistors from the Perspective of Single-Defects

Oxide-defects driven study on reliability and synaptic response characterization of logic devices

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