D IGITAL frequency dividers are of increasing importance in a wide field of device applications for high-speed communication systems and high-end measuring equipment. Ever-increasing frequency limits have led to the demand for GaAs approaches. Dynamic frequency dividers based on 0.2-J.!m GaAs MES-FET's have achieved a 26.5-GHz operational frequency [1]. Operation also at 26.5 GHz was reponed based on 0.25-J.!Tn inverted AIGaAs HEMT technology [2], [3]. High-speed ECL static frequency dividers using Si bipolar transistors, AIGaAs/GaAs hetero bipolar transistors, and AllnAs/InGaAs HBT's have achieved operation at 25 GHz, 34.8 GHz, and 39.5 G Hz. respectively [4)-{6]. A promising technology for AlGaAs/GaAs/AlGaAs quan tum-well transistors with double-delta doped supply layers [7) and gate lengths down to 0.2 JlTn [8) was developed at our institute, for high-speed logic [9], [I 0], analog circuits [II], and optoelectronic lC's I l2]. An integration complexity of 20000 transistors was demonstrated [13]. The design and performance of a dynamic frequency divider operating in the 18-34 GHz range will be presented here.