Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

Abstract

The effects of negative bias temperature instability (NBTI) on the performance of a CMOS inverter have been investigated by means of both simulation and experimental methods. The simulation of NBTI effects on CMOS inverter has been done by shifting the pFET V tho BSIM parameter. The results show that NBTI shifts the inverter transfer curve, reduces the low noise margin and current consumption but increases the high noise margin. A good agreement between simulation and experimental results has been obtained. Therefore, it can be assumed that the effect of NBTI on CMOS circuits can be mainly predicted by shifting the V tho pFET parameter.

Reliability Study of the 90 nm CMOS Inverter

“…From this graph, it shows that the VTC is shifted toward the left hand side after 10 years stress was applied and this is in agreement in a work done by N. Berbel [8]. As the threshold voltage shifts, the maximum gain point also shifts ∆V M as described in the following equation [8]: on which in rcuit delays, hich occurs ion of the (6) d V th is the , it can be e current is n of the µ FE section will e threshold Table 2 shows the maximum gain point shift; ∆V M of the VTC for the simulated inverter and it is observed that the ∆V M increases with stress time for three different temperatures.…”