Modeling the impact of process variation on resistive bridge defects

Abstract

Abstract-Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (V ℎ ) and effective mobility ( ), where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.Index Terms-Resistive bridge fault, process variation, fault model, deep-submicron defect.

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

“…It should be noted that voltage (V ds ) approximation algorithm (Fig. 6) is an improvement over the one presented in [8] and is on average 41-times faster, while achieving the same accuracy. …”

“…III. The voltage approximation algorithm (stage-2 of the proposed technique) is an improvement over the one described in [8]. These two stages therefore determine the values of all parameters needed to determine the logic behaviour of a bridge fault-site at nominal operating conditions.…”

“…Using 350 fault-sites, each with up to 5 driven gates per bridged net, it was shown in [8] that the improvement in critical resistance calculation time reduced to only 10% when using HSPICE for L th generation in comparison to 7-times improvement with a pre-computed L th database. This motivates the need for an efficient logic threshold generation algorithm.…”

“…1, S 1 , S 2 and S 3 ). Bridge defect critical resistance calculation through Shockley transistor model with curve fitting to match SPICE data is accurate only in nominal operating conditions and it loses accuracy under the influence of process variation [8].…”

“…A recent study has reported that it took nearly a week with 8 computers 0000-0000/00$00.00 c 2011 IEEE working in parallel to generate a database for ISCAS 85, 89 benchmarks [9]. See [8] for more details on limitations of available fault modeling techniques.…”