Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation

Abstract

Abstract-Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (V th ) and effective mobility (µ ef f ), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that lowvoltage testing improves detectability of bridge fault; this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.Index Terms-Resistive bridge defects, transition delay test, process variation, logic test, low voltage test.

Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects

“…A bottleneck in simulating additional faults due to process variation with SPICE, is long computation time as observed in recent publications [1], [9], [10], [15]- [17]. Using SPICE with a 65-nm design library, it was reported in [1] that process variation-aware delay fault modeling of a resistive bridge takes on average about 19 minutes per faultsite when using a Quad-Core 2.7 GHz processor with 12 GB RAM. All recent papers [9], [16], [17] have addressed this problem of long computation time through parallel processing by utilizing cluster computing and storing fault simulation data in a database.…”

“…1(a) and (b) are detected at the output of a driven gate either A 1 or A 2 . For resistive bridge defect, Class-I is the most effective test type [1], which is shown in Fig. 1(c).…”

“…Using a 45-nm technology library, an increase in the number of logic faults was observed, and tests generated for nominal operating conditions without considering process variation led to as much as 10% loss of fault coverage [9]. A bottleneck in simulating additional faults due to process variation with SPICE, is long computation time as observed in recent publications [1], [9], [10], [15]- [17]. Using SPICE with a 65-nm design library, it was reported in [1] that process variation-aware delay fault modeling of a resistive bridge takes on average about 19 minutes per faultsite when using a Quad-Core 2.7 GHz processor with 12 GB RAM.…”

“…A recent paper [15] simulated 100 000 samples to analyze the impact of random dopant distribution on transistor threshold voltage by using a cluster of computers. When considering the effect of process variation, recent research has focused on modeling, simulation, and test generation of deep submicrometer defects [1], [9], [10], [13], [14], [16], [17]. Using a 45-nm technology library, an increase in the number of logic faults was observed, and tests generated for nominal operating conditions without considering process variation led to as much as 10% loss of fault coverage [9].…”

“…It is well established that the impact of fabrication process variation on integrated circuit performance and manufacturing test cannot be ignored [1], [10]- [15]. Fabrication process variation is mainly due to subwavelength lithography, random dopant distribution, line edge roughness, and stress engineering [11], [12], [15].…”