Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects

Xu, Xiaopeng; Pramanik, Dipankar; Rollins, Greg

doi:10.1557/proc-0914-f03-03

Cited by 2 publications

(1 citation statement)

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“…The displacements at the line-ends primarily depend on Using the simulated data presented in Table II and the of thermal stress in the metal lines and leads to significantly formalism discussed above, simple analytical compact higher stresses in the conductors, as discussed in [9]. These models to describe the relationship between dielectric effects lead to the formation of stress hotspots, which in turn stresses and interconnect layout parameters for this particular layout are developed.…”

Section: Numerical Analysismentioning

confidence: 99%

A Compact Model Analysis of Layout Variation Impact on Mechanical Stress in Dielectrics

Karmarkar¹,

Saha

et al. 2007

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

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1. Introduction mechanical stress, namely, the difference in the coefficient The current industry trends towards reducing feature of thermal expansion of different materials, intrinsic sources size and increasing integration density call for the use of and external sources like chemical mechanical polishing copper (Cu) metallization and low permittivity (low-k) (CMP), while simulating the stress fields. The simulated interlayer dielectrics (ILD). Low-k dielectrics are typically stress fields are then used to assess the mechanical reliability characterized by low mechanical strength, low hardness and ofthe interconnect structures [7]. high porosity [1]. The thermal mismatch stresses induced by For the cases studied here, the structures are generated the manufacturing process pose significant reliability using mask files in GDSII format and user defined challenges for the integration of Cu/Low-k interconnects processing steps and conditions. The boundary conditions because of the poorer mechanical characteristics of the loware set to reflect a repetitive arrangement of metal lines in k dielectrics [2]. Moreover, the geometry and the pattern of the layout plane. The finite element mesh is defined to the metal lines have a significant impact on the reduce the variation in the simulated stress values due to thermomechanical stresses in multilevel interconnect variation in the mesh parameters. A temperature ramp from structures, which in turn affect the interconnect reliability a stress-free temperature of 250°C to 25°C is simulated to [3], [4]. Interconnect processing, layout geometry and layout assess the thermal mismatch stresses for various layouts [8]. proximity effects can create regions of high stressThe simulated stress fields are analyzed and compact models concentrations and/or gradients in the interconnect structures that describe the impact of layout variation are developed. employed in deep sub-micron technologies. These stress hotspots are responsible for cracking and formation of voids in 3. Results and Discussion metal lines and the surrounding dielectric, thereby A. Layout Proximity Effects decreasing the overall yield [5], [6]. This paper presents a A simple single-level pattern of metal lines embedded in numerical analysis-based compact model approach to low-k dielectric is simulated in this study. Figure 1 (A) improve the manufacturability and reliability (Design for shows the three-dimensional (3D) interconnect structure. Manufacturing) of back-end-of-the-line (BEOL) structures, Figure 1 (B) shows the mask used to generate this structure. with emphasis on the dielectric reliability.

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Section: Numerical Analysismentioning

confidence: 99%