Modeling the effect of technology trends on the soft error rate of combinational logic

Abstract

Abstract

Dependability assessment of by-wire control systems using fault injection

“…Moreover, higher operational frequencies and integration densities combined with the lower power voltages of technologically advanced semiconductor devices make them more susceptible to the effects of neutron and alpha particles [8] [9] [10]. The sources of radiation are cleverly and concisely described in [11].…”

A highly-efficient technique for reducing soft errors in static CMOS circuits

“…The charge deposited is directly related to the energy of the striking particle and soft error rate (SER) increases exponentially with decrease in Qcrit [2]. Soft errors pose increased reliability problems in nanometer-scale circuits because: (1) smaller, faster transistors lower electrical masking effects [1], (2) reduced source/drain capacitances and supply voltages lower Qcrit [3], (3) and higher clock frequencies reduce latching-window masking probability [1]. Recent studies have shown that SER per chip of logic circuits will increase nine orders of magnitude when minimum feature size scales from 600 nm to 50 nm, becoming comparable to SER per chip of unprotected memory elements [1].…”

“…For a SET to cause a soft error, it must propagate to a primary output (PO) gate and be finally captured by an output flip-flop (FF). However, a soft error will not occur if the SET is either: (1) logically masked-some other input of a gate in the SET propagation path determines its output instead of the SET; (2) electrically masked-the SET is attenuated sufficiently due to the electrical properties of gates in the propagation path; or (3) latching-window masked-the SET reaches an output FF, but not at the clock edge where the FF captures the value [1].…”

“…First, we 1 More precisely, a soft error will be caused if the SET pulse overlaps the setup and hold time interval of the output FF. In the above discussion, we exploited the complete slack from t1 till t3 to reduce SER.…”

“…Soft errors pose increased reliability problems in nanometer-scale circuits because: (1) smaller, faster transistors lower electrical masking effects [1], (2) reduced source/drain capacitances and supply voltages lower Qcrit [3], (3) and higher clock frequencies reduce latching-window masking probability [1]. Recent studies have shown that SER per chip of logic circuits will increase nine orders of magnitude when minimum feature size scales from 600 nm to 50 nm, becoming comparable to SER per chip of unprotected memory elements [1]. This necessitates an efficient design approach for static CMOS circuits that would make them soft-error resilient without adversely affecting other design considerations such as power, performance, and cost.…”