Modeling temperature distribution in Networks-on-Chip using RC-circuits

Tockhorn, Andreas; Cornelius, Claas; Saemrow, Hagen; Timmermann, Dirk

doi:10.1109/ddecs.2010.5491779

Cited by 9 publications

(6 citation statements)

References 12 publications

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“…Temperature estimation is performed by capturing the network traffic, using these statistics for estimation of power consumption and computing the temperature profile. The creation of SPICE netlists consisting of RC-circuits in order to model on-chip thermal properties is proposed in (Liu, Calimera, Nannarelli, Macii, & Poncino, 2010) and (Tockhorn, Cornelius, Saemrow, & Timmermann, 2010).…”

Section: Related Workmentioning

confidence: 99%

“…This allows for simultaneous system simulation and thermal modeling, while preserving system integrity (i.e., independence from external tools for power tracing). For modeling, the NoC infrastructure is mapped on a regular grid of RC-tiles (Tockhorn, Cornelius, Saemrow, & Timmermann, 2010). A single RCtile consists of four horizontal and one vertical electrical resistance modeling the resistance for heat flow in the respective direction ( Figure 1).…”

Section: Simulation Environmentmentioning

confidence: 99%

“…As a consequence, thermal stress and physical effects exponentially depending on temperature (JEDEC, 2009) threaten the integrity of Integrated Circuits (ICs) and have major influence on operability, lifetime and performance. The relationship between temperature and deterioration is illustrated by the Arrhenius model (Srinivasan & Adve, 2003) describing the influence of temperature on the velocity of chemical reactions. This model originates from the Van't Hoff rule also known as the reaction rate temperature rule (or RGT rule), saying that chemical reactions take place twice as fast when temperature is increased by 10 K. As a rule of thumb, this also can be interpreted as a bisection of lifetime of ICs with every 10 K temperature increase.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

Wegner

Gag

Timmermann

2012

International Journal of Embedded and Real-Time Communication Systems

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With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

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Section: Related Workmentioning

confidence: 99%

Section: Simulation Environmentmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance Analysis of Temperature Management Approaches in Networks-on-Chip

Wegner

Gag

Timmermann

2012

International Journal of Embedded and Real-Time Communication Systems

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“…Tockhorn et al illustrated thermal behavior of NoC by the thermal model [12]. The basic idea of the thermal model is that, if the cross surface area A and the distance ǻx between tiles are defined, the temperature difference ǻT j between tile j and tile i can be described by equation (2):…”

Section: B Temperature Model and Estimationmentioning

confidence: 99%

Energy and thermal aware mapping for mesh-based NoC architectures using multi-objective ant colony algorithm

Liu

Ying

Lai

et al. 2011

2011 3rd International Conference on Computer Research and Development

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Where IP cores to be mapped must be carefully solved for any given application in order to optimize different performance metrics in Network-on-Chip (NoC) design flow. The optimization of different performance metrics simultaneously may cause a negative effect on each other because of the strong correlation between these performance metrics. In this paper, we propose a multi-objective ant colony algorithm (MOACA) that maps IP cores onto mesh-based NoC architectures. This algorithm is an efficient way to find the pareto-optimal front which optimizes energy consumption and hotspot temperature of NoC. The algorithm has been implemented and evaluated for synthetic generated benchmarks. Experimental results confirm the efficiency, accuracy and scalability of the algorithm.

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“…Another possible application area for ladder circuits refers to the use of electronic RC ladders in modeling of distributed thermal processes (Tockhorn et al 2010). In such a case, the process information flow is represented by the current distribution in the electrical circuit.…”

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confidence: 99%