Modeling split-gate flash memory cell for advanced neuromorphic computing

Tadayoni, M.; Hariharan, S.; Lemke, Steven; Pate-Cazal, T.; Bertello, B.; Tiwari, Vipin; Do, Nhan

doi:10.1109/icmts.2018.8383757

Cited by 5 publications

(2 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition to storage, memristors with multiple analog states are capable of actively processing information, via the so called in-memory computing scheme. In-memory or nearmemory computing with SRAM, DRAM, or flash memory [9,10] provides a highly parallel alternative to resolve the 'memory wall' of the von-Neumann architecture [11] that the data processing and the data storage are separated. This separation results in low efficiency for data-centric tasks due to the high cost of time and energy in data transferring between the memory and the processing units.…”

Section: The Memristormentioning

confidence: 99%

Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Wang

Midya

et al. 2018

J. Phys. D: Appl. Phys.

392

252

View full text Add to dashboard Cite

The memristor is considered as the one of the promising candidates for next generation computing systems. Novel computing architectures based on memristors have shown great potential in replacing or complementing conventional computing platforms based on the von Neumann architecture which faces challenges in the big-data era such as the memory wall. However, there are a number of technical challenges in implementing memristor based computing. In this review, we focus on the research performed on the memristor material stacks and their compatibility with CMOS processes, the electrical performance, and the integration. In addition, recent demonstrations of neuromorphic computing using memristors are surveyed.

show abstract

Section: The Memristormentioning

confidence: 99%

Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Wang

Midya

et al. 2018

J. Phys. D: Appl. Phys.

392

252

View full text Add to dashboard Cite

show abstract

“…Analogue memory-based DNN accelerators are being widely developed in academia and industry using a variety of memories 5 , including resistive RAM (ReRAM) 6,7 , conductive-bridging RAM (CBRAM) 8 , NOR flash [9][10][11][12] , magnetic RAM (MRAM), and phase-change memory (PCM) 13,14 .…”

mentioning

confidence: 99%

Optimized Weight Programming for Analogue Memory-based Deep Neural Networks

Mackin¹,

Rasch²,

An³

et al. 2021

Preprint

View full text Add to dashboard Cite

Analogue memory-based Deep Neural Networks (DNNs) provide energy-efficiency and per-area throughput gains relative to state-of-the-art digital counterparts such as graphic processing units (GPUs). Recent advances focus largely on hardware-aware algorithmic training and improvements in circuits, architectures, and memory device characteristics. Optimal translation of software-trained weights into analogue hardware weights---given the plethora of complex memory non-idealities---represents an equally important goal in realizing the full potential of this technology. We report a generalized computational framework that automates the process of crafting complex weight programming strategies for analogue memory-based DNNs, in order to minimize accuracy degradations during inference, particularly over time. This framework is agnostic to DNN structure and is shown to generalize well across Long Short-Term Memory (LSTM), Convolution Neural Networks (CNNs), and Transformer networks. Being a highly-flexible numerical heuristic, our approach can accommodate arbitrary device-level complexity, and is thus broadly applicable to a variety of analogue memories and their continually evolving device characteristics. Interestingly, this computational technique is capable of optimizing inference accuracy without the need to run inference simulations or evaluate large training, validation, or test datasets. Lastly, by quantifying the limit of achievable inference accuracy given imperfections in analogue memory, weight programming optimization represents a unique and foundational tool for enabling analogue memory-based DNN accelerators to reach their full inference potential.

show abstract

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

Mackin

Tsai

Ambrogio

et al. 2019

Adv Elect Materials

View full text Add to dashboard Cite

large and unavoidable time and energy penalties for data transport between memory and computational blocks-the so-called "von Neumann" bottleneck.Analog hardware accelerators for deep learning can avoid this bottleneck by performing MAC operations in memory using a crossbar array structure. [5][6][7] In these crossbar arrays, nonvolatile memory (NVM) elements are used to encode synaptic weights. This was recently shown capable of 280× speedup in per area throughput while also providing 100× enhancement in per area energy efficiency over state-of-the-art GPUs. [8] While the benefits of speed are readily appreciated, enhancement in energy efficiency can be a powerful driver of purchasing decisions in the data center space as well. [9][10][11][12] Crossbar arrays have been implemented using a variety of analog NVM elements, including resistive RAM (ReRAM), [13,14] conductive-bridging RAM (CBRAM), [15] flash, [16][17][18][19][20] and phase-change memory (PCM). [21,22] However, most NVM device candidates exhibit varying extents of nonideal behavior, including limited resistance contrast, significant nonlinearity in conductance change, as well as strong asymmetry in bidirectional programming. At the application level, this manifests into neural network accuracies that are significantly lower than software-based approaches. Many of these nonidealities, however, can be addressed to an extent through device and circuit-level engineering. One key idea is multiple conductances of varying significance (Figure 1a), where each synaptic weight is distributed across at least two conductance pairs using W = F(G + − G − ) + (g + − g − ). For instance, during training, such a PCM cell could be paired with a capacitive cell to combine complementary features of both and relax the overall device requirements on PCM. [8] In such a scheme, the majority of DNN weight tuning can occur on a linear but volatile 3T1C memory structure, with periodic but infrequent transfer to the PCM cell for nonvolatile storage. Row-(or column-)wise weight transfer also arises in ex situ training and other training variants. Since PCM is subject to the previously mentioned nonidealities, this weight transfer is best performed with a closed-loop iterative tuning procedure with multiple write-plus-read-verify steps to achieve the overall target weight. To avoid performance degradation, particularly during training, NVM programming Crossbar arrays of nonvolatile memory (NVM) can potentially accelerate development of deep neural networks (DNNs) by implementing crucial multiply-accumulate (MAC) operations at the location of data. Effective weight-programming procedures can both minimize the performance impact during training and reduce the down time for inference, where new parameter sets may need to be loaded. Simultaneous weight programming along an entire dimension (e.g., row or column) of a crossbar array in the context of forward inference and training is shown to be important. A framework for determining the optimal hardware conditions in which to program w...

show abstract

Modeling split-gate flash memory cell for advanced neuromorphic computing

Cited by 5 publications

References 2 publications

Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Review of memristor devices in neuromorphic computing: materials sciences and device challenges

Optimized Weight Programming for Analogue Memory-based Deep Neural Networks

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

Contact Info

Product

Resources

About