Modeling solder joint fatigue in combined environmental reliability tests with concurrent vibration and thermal cycling

Abstract

In this paper we discuss the lifetime prediction for Pb-free soldered flip chip components under combined temperature cycling (TC) and vibration loading in terms of the failure mechanisms related to solder joint fatigue. We show the results of several experiments including failure analysis and comparison of lifetime models. For this purpose Finite Element Analyses (FEA) of the thermal cycling and vibration load are carried out and the relevant damage parameters are extracted from these simulations. The results are used in the lifetime models to correlate experimental and predictive results. Shortcomings of the existing life prediction approaches are discussed and ways to improve lifetime prediction are suggested.

Microstructure, isothermal and thermomechanical fatigue behaviour of leaded and lead-free solder joints

“…Furthermore, such an explanation would still not account for the fatigue life being shorter for the OoP than the IP tests. Eckert et al [42,43] studied the fatigue behaviour of solder joints under combined thermal cycling and vibration loading. They have observed that there was a clear interaction effect as the time to failure of BGA solder under combined loading was significantly shorter than that under temperature cycling or vibration alone at room temperature.…”

Reliability improvements in electronic systems by combining condition monitoring approaches

“…Concept of monitoring structures for electro-migration based on results of [5] For the monitoring of flip chip assemblies, which are prone to fail due to the combination of vibration and temperature cycles [6] introduced a specially designed flip chip specimen. [6] showed that those solder joints failed first, which had the highest distance to the neutral point in the middle, Fig. 11.…”

“…11. Example of a monitoring structure for vibration and temperature cycles [6] With increasing miniaturization traditional connection techniques can be replaced by smaller structures. Examples are vias on the wafer level, so-called through-silicon-vias (TSV).…”

Factoring Interacting Stress Mechanisms in Design for Reliability of Extreme Environment Power Modules

“…Yet even beyond this, coupled thermomechanical risk and other failure driving factors like humidity or strain accelerated failure can overlap in system design, leading to premature failures that would be undetected by uni-dimensional accelerated stress testing, typical of those performed in standardsbased qualifications. Several instances of overlapping accelerating stress factors have been noted in literature, where thermal cycling (TC) and vibrations, humidity and TC, or voltage and temperature interact to promote accelerated failure [6][7][8][9][10][11]. For example, EMinduced voids further amplify risk from TC stress with weakened interconnections, so that when considering high current and temperature WBG device interconnects, layout and thermal schemes ought to be evaluated together.…”