Modeling semiconductor devices by using Neuro Space Mapping

Abstract

a b s t r a c tIn this paper a new method for modeling semiconductor devices by use of the drift-diffusion (DD) model and neural networks is presented. Unlike the hydrodynamic (HD) model which is complicated, time consuming with high processing cost, the proposed method has lower complexity and lower simulation time. In this method the RBF neural network has been used for correcting parameters in the drift-diffusion model. Therefore solving approximate model (DD) causes to obtain accurate response. The proposed method is first applied to a silicon n-i-n diode in one dimension, and then to a silicon thin-film MOSFET in twodimensions, both for interpolation and extrapolation. The obtained results for basic variables, i.e., electron and potential distribution for different voltages, confirm the high efficiency of the proposed method.

A two-dimensional analytical model of subthreshold behavior to study the scaling capability of deep submicron double-gate GaN-MESFETs

“…The HDEB model is more accurate than the DD model, but in expense of more complexity and more simulation time, i.e. more simulation cost [5,13].…”

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

“…This method has been investigated in many semiconductor structures and introduced as one of the efficient techniques. [22][23][24] For the first time in this paper, a multi-layer perceptron (MLP) neural network was used to estimate the GNRFET drain current on a nanometer scale. Due to the versatility of the technology, silicon dioxide (SiO 2 ) is chosen as the gate oxide of the desired structure.…”