Modeling Process Variability in Scaled CMOS Technology

FinFET technology is pointed as the main candidate to replace CMOS bulk process in sub-22nm circuits. Predictive technology and design exploration help to understand major effects of variability sources and their impact on circuit performance and power consumption. In this sense, new design methodologies and new EDA tools must be able to deal with the new fabrication process and variability challenges. This paper presents a predictive evaluation of the impact of workfunction variation in the timing and power of standard cells in FinFETs future technology nodes.

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“…These works highlight the deep impact of WFF in threshold voltage and I ON and I OFF currents [5][6][7][8][9][10][11][12][13].…”

Section: Workfunction Fluctuation Impact On Finfetmentioning

confidence: 99%

“…With small feature sizes, low voltages, and complex vector sets, many of these challenges will require new design methodologies and new Electronic Design Automation (EDA) tools to cope with the new fabrication process and variability challenges [6].…”

Section: Introductionmentioning

confidence: 99%

Impact of gate workfunction fluctuation on FinFET standard cells

Meinhardt

Zimpeck

Reis

2014

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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“…Nowadays, there is a demand not only new design methodologies, but also new EDA tools that should be able to deal with the increase in the number and complexity of the design rules and the fabrication process and variability challenges [1] [2]. Parameter variations demand a great effort to create suitable design approaches to deal with power and performance variations.…”

Section: Introductionmentioning

confidence: 99%

A yield-driven regular layout synthesis

Meinhardt

Reis

2013

2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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The continuous devices shrinking has introduced new challenges to integrated circuit design, mainly to deal with the overall yield loss [1]. Designers start to take into account process variability impact in the early design stages to successful deal with yield loss. Process variability have a critical effect on integrated circuits increasing power consumption to out of design specifications, accelerating circuit degradation or introducing erroneous circuit functionality. Routing … This work proposes two main contributions to improve yield: explore regular detailed routing reducing the number of vias and explore new approaches of basic cells in a regular layout synthesis.

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“…The impact of increased device variability is observed in the complexity of the response surface of the drain‐source current, I ds , and transconductance, g m , and so on, of nanoscale devices. Increased variability of critical design quantities requires more advanced modeling approaches . Adding semi‐empirical, empirical, or statistics‐based parameters to analytical device model expressions, as is sometimes performed, reduces intuitive understanding by circuit designers limiting design of variability‐aware circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Traditionally, process corner analysis is used by a designer to characterize circuit variability. Here, sets of worst‐case device models are used in full transient circuit simulation, but this is not a sufficient representation of the actual distribution of important design quantities such as threshold voltage ( V TH ) and saturation current ( I d,sat ) . This is especially true when the relative variability is large.…”

Section: Introductionmentioning

confidence: 99%

Comparison of modeling techniques in circuit variability analysis

Yelten

Franzon

Steer

2011

Int J Numerical Modelling

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SUMMARY Three nonlinear reduced‐order modeling approaches are compared in a case study of circuit variability analysis for deep submicron complementary metal‐oxide‐semiconductor technologies where variability of the electrical characteristics of a transistor can be significantly detrimental to circuit performance. The drain currents of 65 nm N‐type metal‐oxide‐semiconductor and P‐type metal‐oxide‐semiconductor transistors are modeled in terms of a few process parameters, terminal voltages, and temperature using Kriging‐based surrogate models, neural network‐based models, and support vector machine‐based models. The models are analyzed with respect to their accuracy, establishment time, size, and evaluation time. It is shown that Kriging‐based surrogate models and neural network‐based models can be generated with sufficient accuracy that they can be used in circuit variability analysis. Numerical experiments demonstrate that for smaller circuits, Kriging‐based surrogate modeling yields results faster than the neural network‐based models for the same accuracy whereas for larger circuits, neural network‐based models are preferred as, in all metrics, better performance is obtained. Within‐die variations for an XOR circuit are analyzed, and it is shown that the nonlinear reduced‐order models developed can more effectively capture the within‐die variations than the traditional process corner analysis. Copyright © 2011 John Wiley & Sons, Ltd.

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Modeling Process Variability in Scaled CMOS Technology

Cited by 14 publications

References 11 publications

Impact of gate workfunction fluctuation on FinFET standard cells

Impact of gate workfunction fluctuation on FinFET standard cells

A yield-driven regular layout synthesis

Comparison of modeling techniques in circuit variability analysis

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