Modeling of Random Telegraph Noise under circuit operation &amp;#x2014; Simulation and measurement of RTN-induced delay fluctuation

Ito, K.; Matsumoto, Takashi; Nishizawa, Satoshi; Sunagawa, Hiroki; Kobayashi, Kazutoshi; Onodera, Hidetoshi

doi:10.1109/isqed.2011.5770698

Cited by 26 publications

(34 citation statements)

References 9 publications

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“…A random telegraph noise (RTN) signal becomes more prominent in a scaled device [13], [14]. In this letter, we proposed an alternative temperature sensing scheme based on the RTN signals of the contact resistive random access memory (CRRAM) [15]. The distinctive RTN signals on CRRAM devices observed in both the highand low-resistance states (HRS and LRS, respectively) have been reported in our previous study [16].…”

Section: Introductionmentioning

confidence: 87%

Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM

Chang

Huang

Tseng

et al. 2013

IEEE Electron Device Lett.

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A novel contact resistive random access memory (CRRAM) device based a temperature sensor is proposed and investigated in this letter. By establishing the relationship between CRRAM's random telegraph noise (RTN) signal and temperature, a new temperature sensing scheme is demonstrated for the first time. With a simple comparator circuit, a digital output temperature sensor is successfully implemented based on the temperature-dependent RTN signal. The new sensing scheme is very suitable to low-power low-speed sensor modules.Index Terms-Contact resistive random access memory (CRRAM), random telegraph noise (RTN), temperature sensor.

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Section: Introductionmentioning

confidence: 87%

Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM

Chang

Huang

Tseng

et al. 2013

IEEE Electron Device Lett.

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“…Ye et al [13] proposed a two-stage L-shaped circuit to generate RTN signal which is fully compatible with SPICE. The time-domain delay model was used to simulate and measure the fluctuation in [14], but the approach can only applied to simple circuits such as SRAM cell and ring oscillator because of the extraordinary computation complexity. In this paper, the delay characterization of circuit will be investigated, and a fast algorithm will be performed on the circuit-level analysis for RTN.…”

Section: Related Workmentioning

confidence: 99%

“…Though some models which can be integrated into HSPICE analysis are proposed in [11]- [13], the impact of RTN effect on the digital circuits' temporal performance has been rarely studied [14]. Therefore, our contribution in this paper distinguishes itself in the following aspects:…”

Section: Introductionmentioning

confidence: 99%

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

Luo

Wang

Cao

et al. 2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

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“…The impact of single trap induced RTN on memories was widely studied [4], [9]- [15], some circuitlevel simulation approaches were also proposed [16]- [19]. Most of them evaluate single trap induced RTN.…”

Section: Introductionmentioning

confidence: 99%

“…A carrier in the channel is occasionally captured by a trap in the oxide, and the carrier will be emitted back after a period of time. The capture/emission process of a given trap can be described by a two-state Markov chain [16]. With reference to Fig.…”

Section: Introductionmentioning

confidence: 99%

Statistical analysis of random telegraph noise in digital circuits

Chen

Wang

Cao

et al. 2014

2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Random telegraph noise (RTN) has become an important reliability issue at the sub-65nm technology node. Existing RTN simulation approaches mainly focus on single trap induced RTN and transient response of RTN, which are usually time-consuming for circuit-level simulation. This paper proposes a statistical algorithm to study multiple traps induced RTN in digital circuits, to show the temporal distribution of circuit delay under RTN. Based on the simulation results we show how to protect circuit from RTN. Bias dependence of RTN is also discussed.

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Modeling of Random Telegraph Noise under circuit operation — Simulation and measurement of RTN-induced delay fluctuation

Cited by 26 publications

References 9 publications

Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM

Temperature Sensing Scheme Through Random Telegraph Noise in Contact RRAM

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

Statistical analysis of random telegraph noise in digital circuits

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