Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

Mukhopadhyay, Saibal; Mahmoodi, Hamid; Roy, Kaushik

doi:10.1109/tcad.2005.852295

Cited by 384 publications

(234 citation statements)

References 18 publications

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“…Figure 5 illustrates a standard logic design for a SRAM cell consisting of six transistors. Unfortunately, In a static random-access memory (SRAM) cell, a mismatch in the strength between the neighboring transistors, caused by BTI-induced aging, can result in the failure of the cell [21], therefore causing the FPGA logic to malfunction. Specifically, there are mainly three causes of SRAM failure.…”

Section: Bti-induced Error Probability In Sram Cellsmentioning

confidence: 99%

“…For example, suppose the SRAM cell currently stores the value "1", when writing "0" into this cell; the node V L gets discharged through the bit line BL in Fig. 5 to the low value V WR determined by the voltage division between the PMOS P L and the access transistor AX L [21]. If V L cannot be reduced within time below the trip point of inverter P R − N R (V TRIPWR ), the write failure occurs.…”

Section: Bti-induced Error Probability In Sram Cellsmentioning

confidence: 99%

“…In this paper, we adopt the probabilistic SRAM failure model first proposed in [21] in order to analyze and quantify the failure probabilities (access-time failure, read/write failure and hold failure) of synchronous random-access memory (SRAM) cells. Unfortunately, there is no close-form solution for the overall error probability for a given SRAM cell.…”

Section: Bl Blmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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With CMOS technology aggressively scaling towards the 22-nm node, modern FPGA devices face tremendous aging-induced reliability challenges due to bias temperature instability (BTI) and hot carrier injection (HCI). This paper presents a novel anti-aging technique at the logic level that is both scalable and applicable for VLSI digital circuits implemented with FPGA devices. The key idea is to prolong the lifetime of FPGA-mapped designs by strategically elevating the V DD values of some LUTs based on their modular criticality values. Although the idea of scaling V DD in order to improve either energy efficiency or circuit reliability has been explored extensively, our study distinguishes itself by approaching this challenge through an analytical procedure, therefore being able to maximize the overall reliability of the target FPGA design by rigorously modeling the BTI-induced device reliability and optimally solving the V DD assignment problem. Specifically, we first develop a systematic framework to analytically model the reliability of an FPGA LUT (look-up table), which consists of both RAM memory bits and associated switching circuit. We also, for the first time, establish the relationship between signal transition density and a LUT's reliability in an analytical way. This key observation further motivates us to define the modular criticality as the product of signal transition density and the logic observability of each LUT. Finally, we analytically prove, for the first time, that the optimal way to improve the overall reliability of a whole FPGA device is to fortify individual LUTs according to their modular criticality. To the best of our knowledge, this work is the first to draw such a conclusion.

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Section: Bti-induced Error Probability In Sram Cellsmentioning

confidence: 99%

Section: Bti-induced Error Probability In Sram Cellsmentioning

confidence: 99%

Section: Bl Blmentioning

confidence: 99%

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Optimally Fortifying Logic Reliability through Criticality Ranking

et al. 2015

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“…This also applies to the pass transistors that impact the possibility of reading the correct value of a cell. Leakage current during read operations has three components [38]: (a) sub-threshold leakage, (b) gate leakage current and (c) junction leakage current.…”

Section: Dynamic Testsmentioning

confidence: 99%

PPM Reduction on Embedded Memories in System on Chip

Hamdioui

Al-Ars

Jiménez³

et al. 2007

12th IEEE European Test Symposium (ETS'07)

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“…In fast Static Random-Access Memory (SRAM) cells, it induces Static Noise Margin (SNM) variability which causes errors [1,2,3] in some cells when working below Vccmin. Different approaches have been devised to deal with this problem [4,5,6].…”

Section: Introductionmentioning

confidence: 99%

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

Lorente

Valero

Canal

2014

Euro-Par 2013: Parallel Processing Workshops

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Abstract. Unlike other previous techniques, the recently proposed Hard Error Recovery (HER) fault-tolerant cache provides 100% fault-coverage in L1 data caches. This full coverage makes the HER cache appropiate for fault-dominated future technology nodes. An n-way set-associative HER cache implements one cache way with fast SRAM banks and the remaining ways with eDRAM banks to address power and area. Since the number of eDRAM cache blocks used in a specific HER cache organization depends on the cache associativity (i.e., the implemented number of ways), we expect that the performance and energy consumption provided by a given HER cache design strongly depends on the cache geometry. In this work we study the behavior of the HER cache design when applied to a highly associative L1 cache like those found in some modern microprocessors. In particular this work explores a 32KB 8-way associative L1 data cache such as the one used in Intel Haswell microarchitecture. Experimental results show that, at low-power modes compared to a conventional cache with the same storage capacity and number of ways, area, leakage power, and dynamic energy savings of a 4-way HER cache are by 25%, 85%, and 62%, respectively. These percentages are further improved (by 40%, 89%, and 68%, respectively) when the cache associativity is increased to 8 ways, while the performance loss with respect to both an 8-way conventional cache and the 4-way HER cache is minimal.

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Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

Cited by 384 publications

References 18 publications

Optimally Fortifying Logic Reliability through Criticality Ranking

Optimally Fortifying Logic Reliability through Criticality Ranking

PPM Reduction on Embedded Memories in System on Chip

Enhancing Performance and Energy Consumption of HER Caches by Adding Associativity

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