Modeling design constraints and biasing in simulation using BDDs

Yuan, Jianmin; Shultz, Kurt; Pixley, Carl; Miller, Hillel; Aziz, Adnan

doi:10.1109/iccad.1999.810715

Cited by 68 publications

(50 citation statements)

References 9 publications

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“…To improve coverage of the Verilog simulation, a dynamically biased random simulation test bench [19] can also be written directly in ESL scripts.…”

Section: Experiments and Resultsmentioning

confidence: 99%

Executable Protocol Specification in ESL

Clarke

German

et al. 2000

Formal Methods in Computer-Aided Design

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Abstract. Hardware specifications in English are frequently ambiguous and often selfcontradictory. We propose a new logic ESL which facilitates formal specification of hardware protocols. Our logic is closely related to LTL but can express all regular safety properties. We have developed a protocol synthesis methodology which generates Mealy machines from ESL specifications. The Mealy machines can be automatically translated into executable code either in Verilog or SMV. Our methodology exploits the observation that protocols are naturally composed of many semantically distinct components. This structure is reflected in the syntax of ESL specifications. We use a modified LTL tableau construction to build a Mealy machine for each component. The Mealy machines are connected together in a Verilog or SMV framework. In many cases this makes it possible to circumvent the state explosion problem during code generation and to identify conflicts between components during simulation or model checking. We have implemented a tool based on the logic and used it to specify and verify a significant part of the PCI bus protocol.

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“…To improve coverage of the Verilog simulation, a dynamically biased random simulation test bench [19] can also be written directly in ESL scripts.…”

Section: Experiments and Resultsmentioning

confidence: 99%

Executable Protocol Specification in ESL

Clarke

German

et al. 2000

Formal Methods in Computer-Aided Design

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“…Clarke et al further researched the problem of specifications and generators in [20]. However, BDDs were used to demonstrate a practical approach to this problem in the SimGen project [21]. Later on, Shimizu et al [22] [23] automated this approach to verify large industrial designs.…”

Section: Previous Workmentioning

confidence: 99%

Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands

Shekhar

Kalla

Meredith

et al. 2006

2006 Formal Methods in Computer Aided Design

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Abstract-This paper addresses simulation-based verification of highlevel descriptions of arithmetic datapaths. Instances of such designs are commonly found in DSP for audio, video and multimedia applications, where the word-lengths of input/output bit-vectors are fixed according to the desired precision. Initial descriptions of such systems are usually specified as Matlab/C code. These are then automatically translated into behavioural/RTL descriptions (HDL) for subsequent hardware synthesis.In order to verify that the initial Matlab/C model is bit-true equivalent to the translated RTL, how many simulation vectors need to be applied? This paper explores results from number theory and commutative algebra to show that exhaustive simulation is not necessary for testing their equivalence. In particular, we derive an upper bound on the number of simulation vectors required to prove equivalence or identify bugs. These vectors cannot be arbitrarily generated; we determine exactly those vectors that need to be simulated. Extensive experiments are performed within practical CAD settings to demonstrate the validity and applicability of these results.

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“…Our construction technique is most closely related to the stimulus generation algorithm of Yuan et al [19] and the parametric constraint representation of Aagaard et al [1]. Yuan et al present an algorithm which generates random stimuli satisfying a constraint, represented as a BDD, which may depend on state variables of the design.…”

Section: Related Workmentioning

confidence: 99%

“…While the circuit we construct does not reduce the number of input variables compared to the unconstrained circuit, the constraints on the inputs can prevent false error reports that could have occurred if improper input stimuli were allowed to propagate into the module [19]. The constraints may also improve the efficiency of state exploration techniques such as symbolic simulation by reducing BDD sizes [1].…”

Section: Introductionmentioning

confidence: 99%

“…The set of stimuli to be presented to the module, in general or for a particular verification task, may depend on the current state of the module. For example, Yuan et al [19] describe a verification methodology where a module's environment is specified as a constraint which can depend on the state of the module. Jain and Gopalakrishnan's methodology [12] also includes "action" constraints which depend on the system state.…”

Section: Introductionmentioning

confidence: 99%

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Building Circuits from Relations

Kukula

Shiple

2000

Lecture Notes in Computer Science

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Abstract. Given a Free BDD for the characteristic function of an input-output relation T (x, y), we show how to construct a combinational logic circuit satisfying that relation. Such relations occur as environmental constraints for module specifications, as parts of a proof strategies, or can be computed from existing circuits, e.g., by formal analysis of combinational cycles. The resulting circuit C can be used for further analysis, e.g. symbolic simulation, or to reformat a circuit as a logic optimization tactic. The constructed circuit includes supplementary parametric inputs to allow all legal outputs to be generated in the case that T is non-deterministic. The structure of the circuit is isomorphic to that of the BDD for T , and hence is as compact as the BDD. In particular, when T represents a relation between bit vector integer values definable in Presburger arithmetic, the constructed circuit will have a regular bit slice form.

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Modeling design constraints and biasing in simulation using BDDs

Cited by 68 publications

References 9 publications

Executable Protocol Specification in ESL

Executable Protocol Specification in ESL

Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands

Building Circuits from Relations

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