2007
DOI: 10.1109/jssc.2007.900287
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Modeling, Design, and Verification for the Analog Front-End of a MEMS-Based Parallel Scanning-Probe Storage Device

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Cited by 20 publications
(5 citation statements)
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“…The fabrication process is based on a new approach in which the cantilever array is transferred and interconnected to its CMOS counterpart chip on a full wafer-to-wafer basis [17]. The AFE design supports the parallel write and read operations of the cantilevers in the array [21,22]. Specifically, at the input of each cantilever channel is a high-voltage switch matrix that selects the actual operation of the respective cantilever (read, write, or inactive).…”
Section: Device Description and Identificationmentioning
confidence: 99%
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“…The fabrication process is based on a new approach in which the cantilever array is transferred and interconnected to its CMOS counterpart chip on a full wafer-to-wafer basis [17]. The AFE design supports the parallel write and read operations of the cantilevers in the array [21,22]. Specifically, at the input of each cantilever channel is a high-voltage switch matrix that selects the actual operation of the respective cantilever (read, write, or inactive).…”
Section: Device Description and Identificationmentioning
confidence: 99%
“…The analog part of the read channel is implemented in the integrated AFE CMOS chip that includes the complete circuitry to support parallel operation of the cantilevers [21,22]. The design of the on-chip readchannel circuitry allows reliable detection of the tiny signal current obtained with the thermal sensing scheme (DR/R , 10 À3 for a typical indentation).…”
Section: Data Read Channelmentioning
confidence: 99%
“…A lower temperature corresponds to a lower cantilever electrical resistance. An analog front end therefore needs to be able to discriminate between a signal varying between two values of resistance, R, compared to the baseline resistivity, R. The signal-to-noise ratio, or R/R, is less than 10 −3 [61].…”
Section: Analog Front Endmentioning
confidence: 99%
“…Modern circuit design simulation suites (e.g., Spectre™) offer the possibility of simulating arbitrary combinations of high-level hardware-description languages (HDL, e.g., VerilogA, VHDL-AMS, C++ derivatives) together with digital circuitry. The MEMS structures can be incorporated by using equivalent circuit models [149], automatically reducing the complex finiteelement models (FEM) to a multi-domain behavioral model using model-order reduction (MOR) [150]. Although some EDA providers for MEMS design software are starting to offer interfaces to the standard software packages used for CMOS verification (e.g., Coventor [151], Tanner [152]), in most cases custom solutions for verification must be developed.…”
Section: Design Toolsmentioning
confidence: 99%