Modeling and Simulation of Special Shaped SOI Materials for the Nanodevices Implementation

Abstract

In the industrial chain of the nanomaterials for electronic devices, a main stage is represented by the wafer characterization. This paper is starting from a standard SOI wafer with 200 nm film thickness and is proposing two directions for the SOI materials miniaturization, indexing the static characteristics by simulation. The first SOI nanomaterial is a sub-10 nm Si-film with a rectangular shape. The influence of the buried interface fixed charges has to be approached by the distribution theory. The second proposal studies the influence of the vacuum cavity in a “U” shaped SOI nanofilm. In all cases, with rectangular or “U” shape film, the simulations reveal transfer characteristics with a maximum and output characteristics with a minimum for sub-10 nm thickness of the SOI film.

Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

“…In a previous paper, a Silicon On Insulator SOI-MISFET, with a special "U" shape Si-film, was presented, [11]. After a complete removal of the last semiconductor atomic layers, the source -drain conduction region becomes the Nothing Region On Insulator.…”

Introductory Chapter: Green Electronics Starting from Nanotechnologies and Organic Semiconductors

“…These charges are dispersed inside a thin oxide slice. Any SOI device possesses two interfaces: Si-film with BOX, and BOX with Substrate and thirdly the superior interface near gate oxide with Si-film, [18]. The classical model considers the electric charge included in first two interfaces, [15].…”

“…These fixed charges are spatially expanded inside a volume in oxide. In ultrathin SOI structures, consequently this charges can be modeled by a surface charge density, [18].…”

Different Work Regimes of an Organic Thin Film Transistor OTFT and Possible Applications in Bioelectronics

“…Our Organic field effect transistor is related to the Semiconductor on insulator SOI configuration [11] and also corresponds to the Organic Thin-Film Transistors (OTFT), because it uses sub-100nm organic films. Therefore, the back and front gates from SOI architecture [12] are re-named here as bottom and top gates, accordingly to the TFT terminology, [6,7].…”

“…Those parameters that are missing from table 1, for pentacene, organic or insulators, are implicitly included in the Atlas library [13]. The sizes and doping of each layers are selected from a real organic technology [10][11][12][13][14][15][16][17][18][19][20], accordingly with the indicated references from , [14] 1.08 [20] 2x10 -5, [20] p-Pentacene 60…”