Modeling and mitigating NBTI in nanoscale circuits

Khan, Shahzad; Hamdioui, Said

doi:10.1109/iolts.2011.5993802

Cited by 25 publications

(13 citation statements)

References 17 publications

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“…In more detail, PV can be categorized in two main groups: (1) inter-die and (2) intra-die variations [12]. Due to inter-die variations, the same device on a die can have different characteristics across various dies.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

“…Another approach, [11], uses an experimentally verified NBTI model to study DC noise margins in conventional 6T SRAM cells as a function of NBTI degradation in the presence of PVs. Considering functional logic, the authors of [12] propose a transistor sizing technique that not only mitigates NBTI induced delay of the gate under consideration, but also minimizes its impact on the adjacent gates. This technique seems to be very effective, but it is mandatory to identify the critical gates and paths within the circuit in order to apply it.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Gate-level modelling of NBTI-induced delays under process variations

Copetti

Medeiros

Poehls

et al. 2016

2016 17th Latin-American Test Symposium (LATS)

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Continuous technology scaling poses reliability concerns that directly affect the Integrated Circuit's (IC) lifespan. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). Moreover, the impact of NBTI is exacerbated by Process Variation (PV), i.e. variations on transistor attributes during the manufacturing process. In this paper, a hierarchical model to compute NBTI-induced logic path delays at gate level considering PV is proposed. The model is applied in order to identify NBTI-critical logic paths of ICs that are subject to aging mitigation techniques. The model is derived based on intensive SPICE simulations of basic logic gates at transistor level under PV. The experimental results demonstrate an accurate fitting between the analysis performed on the proposed gate-level model and the electrical simulations, while the gate-level analysis provides for several orders of magnitude speedup in simulation.

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Section: Preliminaries and Related Workmentioning

confidence: 99%

Section: Preliminaries and Related Workmentioning

confidence: 99%

Gate-level modelling of NBTI-induced delays under process variations

Copetti

Medeiros

Poehls

et al. 2016

2016 17th Latin-American Test Symposium (LATS)

View full text Add to dashboard Cite

show abstract

“…Another approach [8] uses an experimentally verified NBTI model to study DC noise margins in conventional 6T SRAM cells as a function of NBTI degradation in the presence of process variations. Considering functional logic, the authors of [9] propose a transistor sizing technique that not only mitigates NBTI induced delay of the gate under consideration, but also minimizes its impact on the adjacent gates. This technique seems to be very effective, but it is mandatory to identify the critical gates and paths within the circuit in order to apply such technique.…”

Section: Related Workmentioning

confidence: 99%

SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic

Kostin

Raik

Ubar

et al. 2015

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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Accurate prediction of circuit aging is essential to reliable design, in particular for critical applications. Based on intensive HSPICE electrical simulations, we developed a predictive model to compute NBTI-induced path delay degradation at gate-level. The method is based on a static timing analysis that computes path delay under NBTI-induced V THp (pMOS transistor threshold voltage) degradation. The proposed approach is demonstrated on an industrial ALU circuit design. The obtained results demonstrate a good fitting between the developed model and HSPICE simulations with several orders of magnitude gain in simulation speed.

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“…This method reduces the area penalty of gate-level sizing by an average of 43%. Khan et al studied another transistor-level sizing method that considered the impact of transistor sizing on its adjacent gates [8]. It further reduces the area overhead by 50% as compared with [7].…”

Section: November/december 2013mentioning

confidence: 99%