Modeling and minimization of PMOS NBTI effect for robust nanometer design

Vattikonda, Rakesh; Wang, Wenping; Cao, Yu

doi:10.1145/1146909.1147172

Cited by 316 publications

(137 citation statements)

References 19 publications

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“…As can be seen from the plots in [17], within the ranges of Î values used in ASV, this dependence is fairly linear. Hence, a linearized model is used to capture this second order dependence:…”

Section: E ¡î ø Dependence On Supply Voltagementioning

confidence: 77%

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Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guardbands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

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Section: E ¡î ø Dependence On Supply Voltagementioning

confidence: 77%

“…Previous works [17], [18] have shown that for thinner gate oxides, the amount of degradation due to NBTI increases with an increase in Î . This is caused by increased electric fields that result in higher rates of breakdown of the weak Ë À bonds according to the equations [4], [13]:…”

Section: E ¡î ø Dependence On Supply Voltagementioning

confidence: 90%

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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“…Predictive model for NBTI degradation based on RD framework in case of static NBTI is proposed in [7,10]. These models are also accurate in terms of predicting v th degradation due to NBTI and the simulation results obtained using these models match the experimental data.…”

Section: H H H  (4)mentioning

confidence: 97%

“…This model is incorporated in the model proposed in [9]. Vattikonda et al [10] suggested that non H based mechanisms may have faster response time than the diffusion process and the same is incorporated in the model proposed in [10] by including a constant δ (5 mV) in the stress and recovery equations. The threshold voltage degradation due to NBTI can be estimated using-…”

Section: H H H  (4)mentioning

confidence: 99%

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Dutta

Soni

Pattanaik

2016

IJMECS

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Abstract-Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

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“…Recently, many researchers have studied the NBTI modeling and mitigation techniques on various design abstraction levels. Analytical compact models [6][7][8] that evaluate NBTI effects using power-law timing degradation were proposed to help designers estimate the performance degradation. Based on these transistor compact models, circuit level NBTI degradation analysis models were proposed [9,10].…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

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Modeling and minimization of PMOS NBTI effect for robust nanometer design

Cited by 316 publications

References 19 publications

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

A Review of NBTI Degradation and its Impact on the Performance of SRAM

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

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