Modeling and characterization studies of parasitic elements in lead-on-chip thin-small-outline packaging

Abstract

Porurrietcrs c![fictirig (lie p " t i c eleriieiits of ci Lead-orz-Chip (LOC) Tliirz-Sriinll-OirtliriePackage (TSOP) 'were sttitlieti hy riiotleliiip uith a TI iriterricrl RLC crtrnctor arid riieasitrwiierit technique rtsirig a Vector Network Analyzer (\"A). \70rYtrtiori irz the Resistnrice ( R ) , lriditctpricr ( L ) coid Capacitarice ( C ) of a TSOP with respect to charzges iri the lead rliriierisioris I t w e clssessed Oy riiodelirrg with a lirze-&-space pattern hnsecl on the TSOP georiietry. The effect on KLC d i r e to chc~ripes iii the lecid-to-pimind separation, electrictrl properties 01 the ritaterials arid freqirericy it:ere czssessetl by riiocfehg btrsrd or1 a 54Pirz TSOP applied to 64MOX16 SDRAM. Measiil-eFnerzt was n7ade to corlfirrn the ,fiqiirricy tfepcrrderzcv of RLC ,for Alloy42 (A42), Copper (Cic) arid Pallczdirtrii plated Copper (Pd/Cu) CIS leadfraiize iimtri~icil. Sori~e,friridnriierrtnls.for packagirig desigri 0i.e srriiiiiiarized. For instarice, L caii be reditced bji increasing lead u.it/th tilit/ t/ecwctsirig /ead-io-gi~oitricf separation sirnrt/tcrrieous!\.. hi frequency stdies, it is ,foltnd that A42 ieadfiariie Iicis (I l i i ,~l t r r~r~(~~~~t f~i i c y dr/el'rritlerzc.y of R arid L. Tlziis. electriccllly inferior to those of Cu arid Pd/Cir .