Modeling and Analysis of TSV Noise Coupling Effects on RF LC-VCO and Shielding Structures in 3D IC

Lim, Joonwon; Cho, Jonghyun; Jung, Daniel; Kim, Jonghoon J.; Choi, Sumin; Kim, Dong-Hyun; Lee, Man-Ho; Kim, Joungho

doi:10.1109/temc.2018.2800120

Cited by 14 publications

(6 citation statements)

References 22 publications

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“…Observing the circuit, Equations (14) and (15) are found: By exploiting Equations (13)-(15), the noise V 2 could be expressed in the frequency domain according to V in , then the NILT method can be applied, by replacing F(s) by V 2 (s) in previous equations, to find the noise in the time domain. The voltage source V in is a periodic trapezoidal signal switching expressed by Equation 16.…”

Section: Calculation Of Time-domain Tsv Noise Coupling In 3d-ic Desigmentioning

confidence: 99%

“…Then another transformation from Y g to T g was performed. When finding T g , it is multiplied by T tsv on the left and right sides, and by using Equations (13), (14), and (21) V 2 is found according to V in .…”

Section: Calculation Of Time-domain Tsv Noise Coupling In 3d-ic Desigmentioning

confidence: 99%

“…All these previous works have given models of one TSV without considering general multi-TSV architectures. Thus, in [3,13,14] a TSV noise coupling model and TSV-to-active circuit have been proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using this method, the noise transfer functions in the frequency domain from TSV-to-TSV and TSV-to-active circuit can be estimated.…”

Section: Introductionmentioning

confidence: 99%

“…This technique is based on solving Maxwell's equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. The models proposed in the literature differ; indeed, some models contain the depletion capacitance, TSV resistance, and TSV inductance, others neglect these elements, especially for frequencies below 20 GHs [3,13,14].…”

Section: Introductionmentioning

confidence: 99%

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Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

2019

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Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers.

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Section: Calculation Of Time-domain Tsv Noise Coupling In 3d-ic Desigmentioning

confidence: 99%

Section: Calculation Of Time-domain Tsv Noise Coupling In 3d-ic Desigmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

2019

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“…TSV is insulated by dielectrics to prevent short-circuit between metals and is covered by a thin barrier/seed layer for Cu plating [8][9][10][11]. Different processes have been used to deposit liner, such as thermal oxidation, plasma enhanced chemical vapor deposition (PECVD) and sub-atmospheric chemical vapor deposition (SACVD) [12,13]. Filling TSV is a very critical step for device reliability to ensure high breakdown voltage and low leakage current.…”

Section: Silicon Interposer Productionmentioning

confidence: 99%

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Tian

Liu

2018

Electronics

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Three-dimensional integrated circuits (3D IC) based on TSV (Through Silicon Via) technology is the latest packaging technology with the smallest size and quality. As a result, it can effectively reduce parasitic effects, improve work efficiency, reduce the power consumption of the chip, and so on. TSV-based silicon interposers have been applied in the ground environment. In order to meet the miniaturization, high performance and low-cost requirements of aerospace equipment, the adapter substrate is a better choice. However, the transfer substrate, as an important part of 3D integrated circuits, may accumulate charge due to heavy ion irradiation and further reduce the performance of the entire chip package in harsh space radiation environment or cause it to fail completely. Little research has been carried out until now. This article summarizes the research methods and conclusions of the research on silicon interposers and TSV technology in recent years, as well as the influence of high-energy heavy ions on semiconductor devices. Based on this, a series of research methods to study the effect of high-energy heavy ions on TSV and silicon adapter plates is proposed.Electronics 2018, 7, 112 2 of 29 wafer was invented by M.G Smith et al. [2], which opposite surfaces were connected ohmically to the degenerately doped portions to be electrically connected along the thru-connection. With further research and exploration, 2.5D/3D integration technology with TSV realized integrated circuits with advantages of high interconnection density, high performance, low power consumption, and low cost [3,4]. In addition, the core is widely considered to be the leading technology in the field of high density packaging in the future and is an effective way to break through Moore's Law [5][6][7]. Figure 1. Silicon interposer through electrical copper coating technology production: (a) The construction of through-silicon via on the wafer; (b) The dry film etchant is stuck on the wafer, then exposed and etched; (c) Hole plating and pad fabrication by electroplating methods; (d) The photoresist removing. Adapted with permission from [27], Copyright Elsevier, 2016.

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Multi-chip Modules and Multi-chip Packaging

Božanić

Sinha

2019

Smart Sensors, Measurement and Instrumentation

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Modeling and Analysis of TSV Noise Coupling Effects on RF LC-VCO and Shielding Structures in 3D IC

Cited by 14 publications

References 22 publications

Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

TSV Technology and High-Energy Heavy Ions Radiation Impact Review

Multi-chip Modules and Multi-chip Packaging

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