Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package

Abstract

Abstract-A new hybrid modeling method is proposed for the chip-package comodeling and coanalysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 µm. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package comodeling and simulation of the system-in-package designs.

Genetic Algorithms and Particle Swarm Optimization Mechanisms for Through-Silicon Via (TSV) Noise Coupling

“…is type of noise degrades the circuit performance and makes system sensitivity dominated. It can directly be transmitted to an active circuit via the substrate; therefore, the signal and power are corrupted, the system reliability is reduced, and the bit error rate is increased [21,22]. A TSV is composed of a conductor surrounded by an insulation layer with a very small thickness, which causes an important capacitance between the TSV and the substrate; as a consequence, at high frequencies, a noise can be easily coupled from one TSV to another or substrate and vice versa.…”

Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

“…, z ±k = exp ±j 2πkT τ , and C k = exp(ckT) τ , while τ = NT, ∀k, and z N ±k = exp(± j2πk) = 1. In Equation 12, the first and the third sum are evaluated using the FFT and IFFT algorithms, respectively, while other parts, which present the infinite sum, are used as the input data in the q-d algorithm that uses a very small number of necessary additional terms, as explained in [24]. The computing region should be chosen as:…”

“…This noise degrades system performance and makes it more sensitive. It can also be transmitted directly to an active circuit through the substrate; therefore, the signal and power are corrupted, the system reliability is reduced, and the bit error rate is increased [24,25].…”

Meander-DGS Effect on Electromagnetic Bandgap Structure for Power/Ground Noise Suppression in High-Speed Integrated Circuit Packages and PCBs

“…Power/ground noise, such as simultaneous switching noise (SSN), is a major concern in high-speed circuit designs for achieving high performance and high reliability of electronic systems. As the number of transistors and power consumption of a very large-scale integration (VLSI) increases significantly, power/ground noise severely affects the overall system performance [1][2][3][4]. The power/ground noise produces the problem of glitches, timing push-out of digital signals, and power-supply voltage fluctuations.…”