Model of Secondary ESD for a Portable Electronic Product

Xiao, Jiang; Pommerenke, David; Drewniak, James L.; Shumiya, Hideki; Maeshima, Junji; Yamada, Takashi; Araki, Kiyomichi

doi:10.1109/temc.2011.2171040

Cited by 29 publications

(1 citation statement)

References 25 publications

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“…To increase the robustness of the products against injected ESD noise, different experimental and full-wave numerical modeling techniques for system level ESD coupling analysis have been proposed in the literature. These include: failure analysis using susceptibility testing [5]; analysis of coupled ESD noise to DUT through time and frequency domain measurements [1,[10][11][12][13][14]; and full-wave EM simulation of DUT and ESD source [2,6,[15][16][17][18]. These reported techniques have limitations in terms of the requirement of the manufacturing of the DUT to perform susceptibility analysis [5], or the characterization of the coupled noise at victim positions for each different design configuration of the DUT [10][11][12][13][14]19].…”

Section: Introductionmentioning

confidence: 99%

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes on the high-speed DRAM modules (DDR3 and DDR4) against injected ESD noise are determined through full-wave numerical simulations of the memory modules using the developed 3D model of the ESD gun. The validity of the full-wave numerical setup is confirmed through measurements, prior to the DOE analysis. Besides, current distribution analysis of DRAMs, seven different DOE configurations based on the number of installed decoupling capacitors (decaps) and their values on memory modules, are analyzed. The findings of DOE analysis suggests that DDR4 is less susceptible (70–80 % less) to the coupled ESD noise compared to DDR3. In addition, the command address (CA) nets are most sensitive in both memory modules. The utilization of the maximum possible number of decaps covering low, medium and high frequency ranges, as well as separate power and ground layers in memory stack-up design, increase the robustness and immunity of memory modules for the transient ESD event. The suggested approach offers time-saving and financial advantages to high-speed memory community, with the robust design of the memory products at the design stage before the start of the production phase.

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Section: Introductionmentioning

confidence: 99%

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

et al. 2019

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Effect of spark gap shape on time lag

Wan

Pommerenke²,

Shumiya

et al. 2013

Electron. lett.

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Presented is the effect of sharp spark gap on time lag, which is a very important factor in electrostatic discharge modelling. A long time lag induces a large discharge current and a fast rise time. The large discharge current often causes soft errors in many products. Through measurement and simulation, the relation between sharp edge and time lag is quantified. The result can be used in numerical simulation of breakdown voltage. With the numerical simulation, knowing only the geometry of the spark gap can obtain the discharge current.Introduction: In many products such as cell phones and portable computers, a gap may exist and secondary discharge will occur. Secondary discharge can either upset or damage the product. Secondary discharge [1] is related to the geometry of the gap. The shape of the gap in the product can be complex, but it could be classified as homogeneous or pointed. The pointed gap is non-homogeneous, and the maximum static field strength of the pointed gap is much larger than the homogeneous static field strength. The static field strength has a strong effect on time lag [2], and the time lag is a very important factor in delaying the secondary discharge. With a short time lag, once the charge voltage reaches the threshold voltage, breakdown occurs, and the discharge current is small. With a long time lag, the breakdown is delayed, and finally the charge voltage can be high, and also the discharge current will be large; it can be larger than the IEC standard 61000-4-2 (the standard specifies 3.75 A/kV). Some researchers have investigated the effect of humidity [3] on time lag, but few have studied the effect of gap shape on time lag, which is important in products.

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Effect of secondary discharge on the repeatability of contact discharge method

Wan

Wang

2017

Electron. lett.

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Submillimetre gaps caused by buttons, switches exist in the electronic device. IEC 61000-4-2 indicates that contact discharge method will be used if these floating metals could be touched in its normal use. Secondary discharge happens when conduct contact discharge on these floating metals. The influence of the secondary discharge on the repeatability of contact discharge method using experimental method is analysed. At same applied voltage, the secondary discharge current varies largely, causing bad repeatability. The time lag is the main parameter that influences the secondary discharge greatly. The time lag distribution is also analysed.

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Model of Secondary ESD for a Portable Electronic Product

Cited by 29 publications

References 25 publications

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules

Effect of spark gap shape on time lag

Effect of secondary discharge on the repeatability of contact discharge method

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