Model for hysteresis and kink behavior of MOS transistors operating at 4.2 K

Dierickx, B.; Warmerdam, L.; Simoen, Eddy; Vermeiren, Jan; Claeys, Cor

doi:10.1109/16.3372

Cited by 75 publications

(20 citation statements)

References 17 publications

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“…These phenomena, also present at room temperature but to a lower degree, include interface traps, dopant incomplete ionization, field-assisted ionization, mobility temperature-trend, bandgap temperature-trend, exponential temperature dependency of the intrinsic carrier concentration, and quantum effects. It should be noted that the kink effect in the output characteristics, prominently present in older technologies at cryogenic temperatures [33], has not been observed in this fully-depleted technology below the used supply voltage. Below follows a brief description of the phenomena which can impact a fully-depleted FDSOI technology, and how to model them:…”

Section: Low-temperature Phenomenamentioning

confidence: 75%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The low-temperature transfer characteristics including body-biasing are modeled over a wide temperature range (room temperature down to 4.2 K) using the design-oriented simplified-EKV model. The trends of the free-carrier mobilities versus temperature in long and short-narrow devices are extracted from dc measurements down to 1.4 K and 4.2 K respectively, using a recently-proposed method based on the output conductance. A cryogenic-temperature-induced mobility degradation is observed on long pMOS, leading to a maximum hole mobility around 77 K. This work sets the stage for preparing industrial design kits with physicsbased cryogenic compact models, a prerequisite for the successful co-integration of FDSOI CMOS circuits with silicon qubits operating at deep-cryogenic temperatures.The birth of CMOS-compatible qubits in silicon [1,2,3,4] has rebooted the interest in cryogenic CMOS electronics for computing applications. Since the 1970s, MOSFET devices have been under investigation at cryogenic temperatures for use in custom applications, such as low-noise scientific equipment, spacecraft, power conversion etc. [5,6,7,8,9]. However, despite its many benefits for reaching high-performance and low-power computing [10], cryogenic cooling did not stay into practice for computing, abandoning the trend set by the ETA-10 liquid-nitrogen-cooled supercomputer [11].Nowadays, co-integrating qubits and CMOS circuits on the same substrate can greatly aid the development of scalable quantum computers featuring massive parallelism and error correction [12,13,14]. In this context, a silicon-on-insulator (SOI) platform is particularly attractive since the back gate provides additional control over the electron-spin qubit, trapped under the front gate of a SOI (nanowire) MOSFET[12,15,16]. To integrate the control circuits with quantum devices working at deep-cryogenic temperatures, regular SOI MOSFETs need to demonstrate reliable digital, analog and RF functionalities at such low temperatures. Using SOI cryogenic control electronics, the back gate can prove a useful tool to control the threshold voltage and hence the power consumption in circuits integrated close to the qubits [17], benefiting qubit coherence time by lowering generated noise. The main focus is on advanced ultra-thin body fully-depleted SOI (FDSOI) technology, e.g., the 28-nm node, to enable ultimate scalability of the resulting hybrid quantum-classical system [16,18].The 28-nm node, presently considered the ideal node for analog and RF applications at room temperature [19], has recently been tested for digital and analog functionality down to liquid-helium temperature (4.2 K) [17], and millikelvin temperature (20 mK) [20]. The improvement in RF characteristics has been verified down to liquid-nitrogen temperature (77 K) [21]. In addition to device c...

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Section: Low-temperature Phenomenamentioning

confidence: 75%

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Beckers

Jazaeri

Bohuslavskyi

et al. 2019

Solid-State Electronics

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“…30K for Si, where the thermal energy level is insufficient to ionise dopant atoms. This makes pwell and n-well perform similar to insulators [10]. As temperature lowers, the majority carriers are trapped at source making a bias at the well.…”

Section: Low-temperature Behaviourmentioning

confidence: 95%

Extreme Temperature Electronics - from Materials to Bio-inspired Adaptation

Laketic

Haddow

2007

Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)

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“…[2][3][4] They all achieve an effective resolution of about 8 bits by using successive approximation register (SAR) and flash conversion methods. The main limitation of these methods arises from the highresolution requirement for the comparator, which is more difficult to achieve at cryogenic temperatures because of the anomalies of the MOS transistor characteristics at temperature levels below 30 K. 5 Figure 1 shows a typical drain to source current (I ds ) versus drain-to-source voltage (V ds ) characteristic of a CMOS transistor at 4.2 K. There are two main anomalies: the kink effect and the hysteresis. The kink effect is defined as the sudden increase of I ds when V ds exceeds approximately the mid-supply level.…”

Section: Introductionmentioning

confidence: 99%

A third-order complementary metal–oxide–semiconductor sigma-delta modulator operating between 4.2 K and 300 K

Okcan

Gielen

Hoof

2012

Review of Scientific Instruments

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This paper presents a third-order switched-capacitor sigma-delta modulator implemented in a standard 0.35-μm CMOS process. It operates from 300 K down to 4.2 K, achieving 70.8 dB signal-to-noise-plus-distortion ratio (SNDR) in a signal bandwidth of 5 kHz with a sampling frequency of 500 kHz at 300 K. The modulator utilizes an operational transconductance amplifier in its loop filter, whose architecture has been optimized in order to eliminate the cryogenic anomalies below the freeze-out temperature. At 4.2 K, the modulator achieves 67.7 dB SNDR consuming 21.17 μA current from a 3.3 V supply.

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Model for hysteresis and kink behavior of MOS transistors operating at 4.2 K

Cited by 75 publications

References 17 publications

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Characterization and modeling of 28-nm FDSOI CMOS technology down to cryogenic temperatures

Extreme Temperature Electronics - from Materials to Bio-inspired Adaptation

A third-order complementary metal–oxide–semiconductor sigma-delta modulator operating between 4.2 K and 300 K

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