Model-Driven Approach for Automatic Dynamic Partially Reconfigurable IP Customization

Abstract

This paper presents a framework which automates the generation of DPR capable IP cores. The approach is based in an MDE methodology, which exploits two widely used standards for Systems-on-Chip specification, UML/MARTE and IP-XACT. The approach aims at generating IPs which incorporate different functionalities by using code templates. The templates correspond to IP-XACT components that represent VHDL modules to be implemented in the IP. The IP-XACT subsystem description is generated from the MARTE description, effectively diminishing the complexity of creating this kind of systems by increasing the level of abstraction. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. A model for the DPR IP is presented and a case study for a simple IP is presented. The use of our MDE approach is introduced to demonstrate how the generation from MARTE to EDK systems is performed.

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

“…Depending on the type of CE, some might require to be set at this stage, whereas others are to be configured by external tools in the flow. The way different IP-XACT concepts are used in our methodology will be further discussed in Section 4; the mapping between MARTE and IP-XACT objects can be found in previous work [13].…”

Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation

“…Managing such a complex reconfigurable system with a large variety of transcoding scenarios requires new validation methods and tools in early design stage. Several attempts have been proposed to model partial dynamic reconfiguration [4], [5]. However, none of these approaches have dealt with the challenges cited above particularly with the IP integration and reuse in dynamic reconfigurable systems.…”