Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation

Abstract

Video adaption is one of the main solutions to offer access to the large array of existing multimedia contents and the variety of terminals and networks. This adaptation can be achieved efficiently using transcoding techniques. The implementation of the various adaptation possibilities and techniques in embedded systems such as home gateway requires flexible and efficient architectures. This paper presents a hardware reconfigurable architecture for the real time adaptation of video contents for different terminals and available bandwidth. This architecture is designed to adapt a compressed stream in advanced video coding standard (H264/AVC) and/or MPEG-2. A system level model of reconfigurable transcoder is developed for IP integration and architectural exploration by taking into account dynamic and partial reconfiguration. The developed simulation model of dynamic partial reconfiguration allowed the early estimation of performances and the design of the suitable solution for the considered transcoding scenarios.