Mobility Enhancement in Amorphous In-Ga-Zn-O Thin-Film Transistor by Induced Metallic in Nanoparticles and Cu Electrodes

Hu, Shiben; Ning, Honglong; Lu, Kuankuan; Fang, Zhiqiang; Li, Yuzhi; Yao, Rihui; Xu, Miao; Wang, Lei; Peng, Junbiao; Lu, Xubing

doi:10.3390/nano8040197

Cited by 20 publications

(16 citation statements)

References 23 publications

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“…The ALD growth step for the Al 2 O 3 gate insulator requires subjecting the already‐deposited IGZO layer to vacuum as well as chemical precursors which may change the properties of the surface. Most notably, this may result in the formation of indium nanoparticles and/or the adsorption of OH − at the surface of the semiconductor, with the net effect of increasing the conductivity of the IGZO layer at this interface. Inserting a barrier SiO 2 layer between IGZO and ALD Al 2 O 3 , for instance, may improve the device operation.…”

Section: Structural and Electrical Characteristics Of Source‐gated Trmentioning

confidence: 99%

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

et al. 2019

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Thin insulating layers are used to modulate a depletion region at the source of a thin‐film transistor. Bottom contact, staggered‐electrode indium gallium zinc oxide transistors with a 3 nm Al2O3 layer between the semiconductor and Ni source/drain contacts, show behaviors typical of source‐gated transistors (SGTs): low saturation voltage (VD_SAT ≈ 3 V), change in VD_SAT with a gate voltage of only 0.12 V V−1, and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry: the saturated current changes only 0.15× for 2–50 µm channels and 2× for 9‐45 µm source‐gate overlaps. A higher than expected (5×) increase in drain current for a 30 K change in temperature, similar to Schottky‐contact SGTs, underlines a more complex device operation than previously theorized. Optimization for increasing intrinsic gain and reducing temperature effects is discussed. These devices complete the portfolio of contact‐controlled transistors, comprising devices with Schottky contacts, bulk barrier, or heterojunctions, and now, tunneling insulating layers. The findings should also apply to nanowire transistors, leading to new low‐power, robust design approaches as large‐scale fabrication techniques with sub‐nanometer control mature.

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Section: Structural and Electrical Characteristics Of Source‐gated Trmentioning

confidence: 99%

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

et al. 2019

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“…On the other hand, with displays with high resolution (≥8 K), high frame-rate (≥480 Hz) and large size (≥110 inches) becoming increasingly popular, copper (Cu) is considered to be the most promising electrode material in TFTs due to its low resistivity, good thermal stability, high thermal conductivity and good electromigration reliability [ 14 , 15 ]. As the source and drain (S/D) electrodes have direct contact with the semiconductor layer, the contact characteristics between them are very important in the research of TFTs with Cu S/D electrodes.…”

Section: Introductionmentioning

confidence: 99%

Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

Zhang

et al. 2021

Membranes

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High-performance amorphous oxide semiconductor thin film transistors (AOS-TFT) with copper (Cu) electrodes are of great significance for next-generation large-size, high-refresh rate and high-resolution panel display technology. In this work, using rare earth dopant, neodymium-doped indium-zinc-oxide (NdIZO) film was optimized as the active layer of TFT with Cu source and drain (S/D) electrodes. Under the guidance of the Taguchi orthogonal design method from Minitab software, the semiconductor characteristics were evaluated by microwave photoconductivity decay (μ-PCD) measurement. The results show that moderate oxygen concentration (~5%), low sputtering pressure (≤5 mTorr) and annealing temperature (≤300 °C) are conducive to reducing the shallow localized states of NdIZO film. The optimized annealing temperature of this device configuration is as low as 250 °C, and the contact resistance (RC) is modulated by gate voltage (VG) instead of a constant value when annealed at 300 °C. It is believed that the adjustable RC with VG is the key to keeping both high mobility and compensation of the threshold voltage (Vth). The optimal device performance was obtained at 250 °C with an Ion/Ioff ratio of 2.89 × 107, a saturation mobility (μsat) of 24.48 cm2/(V·s) and Vth of 2.32 V.

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“…However, several reports have been revealed that the diffusion of Cu into IGZO deteriorates the electrical performance because it is acting as acceptor-like trap states of IGZO TFT [11]- [15]. Recently, a low resistance stacked structure of S/D on IGZO was introduced to enhance the contact properties [16]- [18]. The Ti and Mo has used widely as an interfacial layer to protect the Cu diffusion into IGZO and to reduce the impact of the Schottky barrier.…”

Section: Introductionmentioning

confidence: 99%

Back-channel Etched In-Ga-Zn-O Thin-film Transistor Utilizing Selective Wet-Etching of Copper Source and Drain

Khan¹,

Mab²,

Hattori³

2021

Preprint

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The electrical performance of the back-channel etched Indium–Gallium–Zinc–Oxide (IGZO) thin-film transistors (TFTs) with copper (Cu) source and drain (S/D) which are patterned by a selective etchant was investigated. The Cu S/D were fabricated on molybdenum (Mo) layer to prevent the Cu diffusion to the active layer (IGZO). We deposited the Cu layer using thermal evaporation and performed the selective wet etching of Cu using non-acidic special etchant without damaging the IGZO active layer. We fabricated the IGZO TFTs and compare the performance in terms of linear and saturation region mobility, threshold voltage and ON current (ION). The IGZO TFTs with Mo/Cu S/D exhibits good electrical properties as the linear region mobility is 12.3 cm2/V-s, saturation region mobility is 11 cm2/V-s, threshold voltage is 1.2 V and ION is 3.16 x 10-6 A. We patterned all the layers by photolithography process. Finally, we introduced SiO2-ESL layer to protect the device from the external influence. The results show that the prevention of Cu and introduced ESL layer enhances the electrical properties of IGZO TFTs.

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Mobility Enhancement in Amorphous In-Ga-Zn-O Thin-Film Transistor by Induced Metallic in Nanoparticles and Cu Electrodes

Cited by 20 publications

References 23 publications

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Amorphous NdIZO Thin Film Transistors with Contact-Resistance-Adjustable Cu S/D Electrodes

Back-channel Etched In-Ga-Zn-O Thin-film Transistor Utilizing Selective Wet-Etching of Copper Source and Drain

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