Mobile ion contamination in CMOS circuits: a clear and present danger

Abstract

The struggle against positive mobile ionic contamination (PMIC) in integrated circuit devices continues in spite of the tremendous gains in the purity of Semiconductor Grade starting materials. As device geometries have decreased and levels of integration have increased, package types have multiplied. Highly sophisticated analytical techniques are required to unambiguously identify the specific ions causing a particular single transistor to fail. The monitoring of VLSI wafer manufacturing and packaging process steps to assure minimal residual positive ionic contaminants takes greater efforts as the level of device-killing contaimination decreases. This tutorial presented analytical case studies for the unambiguous identification of failure-causing metal ionic contamination.The impact of PMIC on MOS devices and circuits was also discussed. The problems caused by the collection of PMIC near active devices include negative VT shifts in active and parasitic NMOSFET devices as well as increased leakage in PMOS devices. The effect of lowering the VT of an NMOS transistor results in an increased off state leakage current.In circuits the instabilities associated with PMIC are typically found after static lifetest and burn-in stresses performed at elevated temperatures. The circuits which are most susceptible to PMIC failures are those which have small restoring currents. SRAM circuits fabricated using a 4T NMOS cell with polysilicon load resistors, of approximately 10 GigaOhms to 1 TeraOhm are susceptible to this failure mechanism. Electrical failure analysis on devices with PMIC typically consists of bit mapping and microprobing failing arrays on devices before and after bake recovery. A case study of an SRAM failure analysis was given which showed the shifts of NMOS device characteristics at several measurement points during a bake recovery experiment. The results of this study show that the active NMOS transistors had shifted VT's which caused leakage currents from the SRAM storage node. Another SRAM case study was presented which characterized a bake recoverable failure mechanism which was not due to PMIC contamination, but was caused by polysilicon stringers. This last case study was given to show that bake recoverable failure mechanisms are not always due to IPMIC. complex multilayer imetalization (MLM) are increasingly susceptible to positive mobile ion contamination. A nondestructive, low cost electrical method for monitoring PMIC in MLlM structures is very desirable. Electrical measurements of mobile ion contamination in integrated circuit processing are typiciilly performed on a MOS capacitor using CV bias-temperature stressing or the triangular voltage sweep (TVS) technique. An advantage of TVS is that it does not specifically require a MOS capacitor. This allows the TVS method to be extendled to multilevel metalization structures. Advanced CMOS and BiCMOS technologies withThe capacity atf TVS for measuring mobile ions in a variety of practical MLM structures including metal-1 edge intensive, metal-2 edge inte...

Synthesizing the biochemical and semiconductor worlds: the future of nucleic acid nanotechnology

“…First, the cations necessary for nucleic acid selfassembly would, if present during fabrication, destroy the electrical properties of most semiconductor devices. 34 Second, NAN assembly occurs at, or within a few kT of, thermodynamic equilibrium, under which conditions the defect percentage is high, [35][36][37] greater than one in 10 2 , and scales poorly with size. 38,39 The intrinsic defectivity of NAN makes it a poor choice for leadingedge nanoelectronic fabrication, in which defect levels are, and must be, routinely less than one in 10 12 .…”