MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP

Abstract

It is difficult to improve the single-thread performance of a processor in memory-intensive programs because processors have hit the memory wall, i.e., the large speed discrepancy between the processors and the main memory. Exploiting memory-level parallelism (MLP) is an effective way to overcome this problem. One scheme for exploiting MLP is aggressive out-of-order execution. To achieve this, large instruction window resources (i.e., the reorder buffer, the issue queue, and the load/store queue) are required; however, simply enlarging these resources degrades the clock cycle time. While pipelining these resources can solve this problem, this leads to instruction issue delays, which prevents instructionlevel parallelism (ILP) from being exploited effectively. As a result, the performance of compute-intensive programs is degraded dramatically.This paper proposes an adaptive dynamic instruction window resizing scheme that enlarges and pipelines the window resources only when MLP is exploitable, and shrinks and de-pipelines the resources when ILP is exploitable. Our scheme changes the size of the window resources by predicting whether MLP is exploitable based on the occurrence of last-level cache misses. Our scheme is very simple and hardware change is accommodated within the existing processor organization, it is thus very practical. Evaluation results using the SPEC2006 benchmark programs show that, for all programs, our dynamic instruction window resizing scheme achieves performance levels similar to the best performance achieved with fixed-size resources. On average, our scheme produces a performance improvement of 21% in comparison with that of a conventional processor, with an additional cost of only 6% of the conventional processor core or 3% of the entire processor chip, thus achieving a significantly better cost/performance ratio that is far beyond the level * Presently with Transportation Bureau, City of Nagoya † Presently with Renesas Electronics Corporation that can be achieved based on Pollack's law. The evaluation results also show an 8% better energy efficiency in terms of 1/EDP (energy-delay product).

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control

“…2, DIWR achieves significant performance improvements. Also, as shown in [2], [3], energy efficiency is improved, mainly because execution time is significantly reduced. Unfortunately, power consumption increases owing to the enlarged instruction window.…”

“…The pipeline depth of each resource is based on that in [2], [3]. In Table 3, we also include the assumption of the penalty at level transition [2], [3].…”

“…This is mainly due to pipelining the IQ, which prevents dependent instructions from being issued back-to-back. To solve this problem, Kora et al proposed dynamic instruction window resizing (DIWR), which appropriately configures the size of the instruction window to the available parallelism (MLP or ILP) [2], [3]. During a period where MLP is valuable to performance, the instruction window size is enlarged, whereas during a period where ILP is valuable, it is reduced.…”

FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors

“…To do so, they employ a number of large, complex, and power-hungry hardware structures such as the instruction queue (IQ), physical register files (PRF), and load/store queues (LSQ). The IQ is responsible for identifying and selecting ready instructions for execution, and is arguably the most complex and power-intensive [1], [2] structure. Its complexity stems mainly from two sources: First, as instructions complete their execution, the IQ needs to broadcast their results (destination register or instruction id) to all other waiting instructions.…”

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

“…This paper is an extension of our previous conference paper [7], evaluating the scheme with a more optimized configuration and providing additional evaluation results.…”