Mixed-Signal Neuromorphic Inference Accelerators: Recent Results and Future Prospects

Bavandpour, Mohammad; Mahmoodi, Mohammad Reza; Nili, Hussein; Bayat, F. Merrikh; Prezioso, M.; Vincent, Adrien F.; Strukov, Dmitri B.; Likharev, K. K.

doi:10.1109/iedm.2018.8614659

Cited by 33 publications

(29 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In contrast to the hardware experiment, the weight refresh operation was distributed across training examples as opposed to periodically refreshing the whole array during training, which allowed it to be performed in parallel with the weight update computation in the digital unit (see Supplementary Note 8). These optimizations resulted in 139× improvement in the energy consumption of the (Bavandpour et al, 2018;Marinella et al, 2018;Chang et al, 2019;Park et al, 2019;Hirtzlin et al, 2020). For training, our approach compares favorably with a digital spiking neural network (254.3 nJ/image) (Park et al, 2019) and is also close to an analogonly approach using 3T1C+PCM synaptic devices (48 nJ/image) (Chang et al, 2019).…”

Section: Discussionmentioning

confidence: 83%

Mixed-Precision Deep Learning Based on Computational Memory

et al. 2020

View full text Add to dashboard Cite

Section: Discussionmentioning

confidence: 83%

Mixed-Precision Deep Learning Based on Computational Memory

et al. 2020

View full text Add to dashboard Cite

“…𝐼 𝑖𝑗 = 𝐼 𝑚𝑖𝑛 + 𝑤 𝑖𝑗 (𝐼 𝑚𝑎𝑥 − 𝐼 𝑚𝑖𝑛 ) (iii) Each column of the programmable current sinks is connected to a load capacitor 𝐶 𝑗 . A threshold (neuron) circuit proposed in [14] with a transfer function given as:…”

Section: Proposed Vmm Approachmentioning

confidence: 99%

Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays

Sahay

Bavandpour

Mahmoodi

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

The emerging mobile devices in the era of Internet-of-Things (IoT) require a dedicated processor to enable computationally intensive applications such as neuromorphic computing and signal processing. Vector-by-matrix multiplication is the most prominent operation in these applications. Therefore, there is a critical need for compact and ultralow-power vector-by-matrix multiplier (VMM) blocks to perform resource-intensive low-to-moderate precision computations. To this end, in this article, we propose a timedomain mixed-signal VMM exploiting a modified configuration of 1MOSFET-1RRAM (1T-1R) array. The proposed VMM overcomes the energy inefficiency of the current-mode VMM approaches based on RRAMs. A rigorous analysis of different nonideal factors affecting the computational precision indicates that the nonnegligible minimum cell currents, channel length modulation (CLM), and drain-induced barrier lowering (DIBL) are the dominant mechanisms degrading the precision of the proposed VMM. We also show that there exists a tradeoff between the computational precision, dynamic range, and the area-and energy-efficiency of the proposed VMM approach. Therefore, we provide the necessary design guidelines for optimizing the performance. Our preliminary results indicate that an effective computational precision of 6 bits is achievable owing to the inherent compensation effect in the modified 1T-1R blocks. Furthermore, a 4-bit 200 × 200 VMM utilizing the proposed approach exhibits a significantly high energy efficiency of ∼1.5 Pops/J and a throughput of 2.5 Tops/s including the contribution from the input/output (I/O) circuitry. INDEX TERMS 1T-1R array, mixed-signal VMM, time-domain encoding, vector-by-matrix multiplication. I. INTRODUCTION

show abstract

“…The main downside of such circuits is lower input / output impedance, which leads to larger VMM peripheral overhead, especially for memory devices with larger conductances. However, such overhead can be reduced via efficient sharing of peripheral resources, at the cost of decreasing computational throughput [27,28], which should be acceptable given the very high speed of memristor-based VMMs [29].…”

Section: Introductionmentioning

confidence: 99%

4K-memristor analog-grade passive crossbar circuit

et al. 2021

View full text Add to dashboard Cite

The superior density of passive analog-grade memristive crossbar circuits enables storing large neural network models directly on specialized neuromorphic chips to avoid costly off-chip communication. To ensure efficient use of such circuits in neuromorphic systems, memristor variations must be substantially lower than those of active memory devices. Here we report a 64 × 64 passive crossbar circuit with ~99% functional nonvolatile metal-oxide memristors. The fabrication technology is based on a foundry-compatible process with etch-down patterning and a low-temperature budget. The achieved <26% coefficient of variance in memristor switching voltages is sufficient for programming a 4K-pixel gray-scale pattern with a <4% relative tuning error on average. Analog properties are also successfully verified via experimental demonstration of a 64 × 10 vector-by-matrix multiplication with an average 1% relative conductance import accuracy to model the MNIST image classification by ex-situ trained single-layer perceptron, and modeling of a large-scale multilayer perceptron classifier based on more advanced conductance tuning algorithm.

show abstract

Mixed-Signal Neuromorphic Inference Accelerators: Recent Results and Future Prospects

Cited by 33 publications

References 14 publications

Mixed-Precision Deep Learning Based on Computational Memory

Mixed-Precision Deep Learning Based on Computational Memory

Energy-Efficient Moderate Precision Time-Domain Mixed-Signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays

4K-memristor analog-grade passive crossbar circuit

Contact Info

Product

Resources

About