Mitigating Soft Errors in Processors Cores Embedded in System-on Programmable-Chips

On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

“…Special purpose hardware cores can be used to assist fault detection as in the case of Watchdog Timers (WDTs) and Watchdog Processors (WDPs) [8][9]. Esposito and Violante [10], proposed an architecture based on a combination of WDPs and WDTs focused on space applications. The proposed architecture used software and hardware means for detecting errors and implemented tolerance to transient faults by redundancy of execution.…”

“…Each signature is associated to a block in the program, defined as a portion of software with a singled entry and a single exit. A WDT is also used in the architecture described in Avramenko et al [10] to recover from Single Event Functional Interruptions (SEFIs) and from permanent errors. The software is in charge of resetting the WDT within a given timeout, otherwise the system is reset and a signal is sent to the external interface in order to allow a redundant computer to provide correct outputs to the user.…”

“…The software is in charge of resetting the WDT within a given timeout, otherwise the system is reset and a signal is sent to the external interface in order to allow a redundant computer to provide correct outputs to the user. Avramenko et al [10] evaluated the architecture through fault injection simulation experiments.…”

“…The architecture proposed in this paper, is built on top of the one proposed by Esposito and Violante [10] and uses results of Avramenko et al [11] with some additions and modifications. This paper is an extension of Esposito et al [12].…”

On the consolidation of mixed criticalities applications on multicore architectures

“…The architecture proposed in this paper, is built on top of the one proposed by Esposito and Violante [10] and uses results of Avramenko et al [11] with some additions and modifications. This paper is an extension of Esposito et al [12].…”