On the Consolidation of Mixed Criticalities Applications on Multicore Architectures

Abstract

In this paper we propose a hybrid solution to ensure results correctness when deploying several applications with different safety requirements on a single multi-core-based system. The proposed solution is based on lightweight hardware redundancy, implemented using smart watchdogs and voter logic, combined with software redundancy. Two techniques of software redundancy are used: the first one is software temporal triple modular redundancy, used for those tasks with low criticality and no real-time requirement. The second software redundancy technique is triple module redundancy for tasks with high criticality and real-time requirements, assisted by a hardware voter. A hypervisor is used to separate each task in the system in an independent resource partition, thus ensuring that no functional interference is occurring. The proposed solution has been evaluated through hardware and software fault injection on two hardware platforms, featuring a dual-core processor and a quad-core processor respectively. Results show a high fault tolerance achieved using the proposed architecture.

System-level architecture for mixed criticality applications on MPSoC: A space application

“…Both Control and Vision are periodic tasks. In [1], the architecture proposed did not feature the software modifications later introduced in [13], we refer to this as the P+CFC solution, where P stands for partitioning and CFC refers to the Control Flow Check technique implemented through the Watchdog Processor IP. In the Complete solution, the Control application is implemented in a TMR scheme, whereas the Vision application is implemented in a DT2+TTMR scheme.…”

“…In this paper we use results from radiation experiments and fault injection simulation to evaluate the dependability of a COTS-based multicore system architecture implementing hybrid fault tolerance solutions. The architecture was proposed in [1] and extended in [13]. Both papers were based on the implementation of a fault tolerant system on a dual-core architecture, with fault injection simulation results suggesting their effectiveness.…”

“…In this section, we briefly describe the architecture presented in [1] and [13], for which the dependability analysis is performed. The system is composed of a multi-processor system-on-chip (MPSoC) and a companion chip.…”

A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles

“…The hybrid architecture proposed by Avramenko et al [4] uses a hypervisor to avoid low-criticality applications from corrupting the high-criticality applications. Esposito et al [12] designed a system that allows the consolidation of different applications with different safety and performance requirements on the same chip. On the other hand, temporal partitioning allows different applications to share core resources in a time-multiplexing way.…”

Deterministic network on chip for deploying real time applications on many-core processors

“…To face lack of information, authors of [5] suggest that the availability of necessary information should be a selection criterion when choosing the hardware platform. A solution for shared memory can be resource partitioning by means of a type-1 hypervisor [12][13] [14]. A type-1 hypervisor with support for multi-core architectures can implement partitioning by assigning a single core as a resource to a given partition.…”