Minimizing the Power Consumption of an Asynchronous Multiplier

Liu, Yijun; Furber, Steve

doi:10.1007/978-3-540-30205-6_31

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E Fine-grain Clock Gating1

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2007

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“…1. An asynchronous pipeline using a code-data coding low-power multiplier [14] and the synchronous implementation has the same architecture. The 32 × 32-bit iterative multiplier has two pipeline stages, the first adds 8 partial products together while the second iterates the result, adds the value from the first stage, then shifts the sum right 8 bits.…”

Section: E Fine-grain Clock Gatingmentioning

confidence: 99%

Power-Efficient Asynchronous Design

Liu

Chen

et al. 2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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The potential advantage of low power consumption is one of the main reasons why asynchronous logic attracts attention from both industrial and academic circles. A number of low-power asynchronous designs have been proposed since the 1990s. In this paper, an attempt is made to compare the power-efficiency of asynchronous and synchronous designs, and to evaluate low-power asynchronous techniques.20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00 © 2007 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00

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Section: E Fine-grain Clock Gatingmentioning

confidence: 99%