Minimizing the cost of iterative compilation with active learning

William, F Ogilvie; Petoumenos, Pavlos; Wang, Zheng; Leather, Hugh

doi:10.1109/cgo.2017.7863744

Cited by 39 publications

(15 citation statements)

References 54 publications

(63 reference statements)

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“…Ashouri et al [Ashouri et al 2014] empregam uma rede Bayesiana para criar um modelo capaz de prever um bom plano de compilação para uma determinada aplicação, com um tempo de busca melhor que aos tradicionais autotunings que utilizam métodos mais simples de busca. Ogilvie et al [Ogilvie et al 2017] empregam aprendizagem ativa para criar um modelo de predição de planos de compilação, que minimize a quantidade de vezes que um plano precisa ser avaliado. Embora tais trabalhos apresentem resultados significativos, ainda existe a necessidade de avaliar diversos planos de compilação para descobrir o melhor.…”

Section: Trabalhos Relacionadosunclassified

Predição de Desempenho com Graph Neural Networks

Rosário

Zanella²,

Silva³

et al. 2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

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Melhorar o desempenho de uma aplicação em computadores modernos envolve escolhas em um largo espaço de busca, pois tais arquiteturas possuem variadas características que impactam signiﬁcativamente o desempenho das aplicações. Além disso, diferentes aplicações tendem a utilizar essas características de forma diferente, tornando a função que mapeia o desempenho de uma aplicação em um hardware bastante complexa. O que torna a tarefa de gerar códigos que maximizem tal função, por parte de compiladores ou especialistas, uma tarefa difícil. Uma possibilidade é avaliar automaticamente várias possibilidades de compilação, técnica conhecida como autotuning. Porém, o custo de executar a aplicação para medir seu desempenho para cada possibilidade tem um elevado custo. Por isso, é comum a utilização de preditores de desempenho para acelerar essa exploração. Nesse trabalho, implementamos e avaliamos o uso de redes neurais de grafos, mais especiﬁcamente redes convolucionais de grafos, para a tarefa de predizer o desempenho de uma aplicação. Nós treinamos uma rede com 30 mil diferentes planos de compilação aplicados em 300 diferentes aplicações e mostramos que redes baseadas em grafo podem aprender sobre as características do grafo de ﬂuxo de controle, obtendo desempenho melhor do que técnicas que não consideram tal grafo durante a predição de desempenho.

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Section: Trabalhos Relacionadosunclassified

Predição de Desempenho com Graph Neural Networks

Rosário

Zanella²,

Silva³

et al. 2020

Anais Do XXI Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2020)

View full text Add to dashboard Cite

show abstract

“…Machine learning has been employed for various optimization tasks [40], including code optimization [7,12,29,30,37,39,41,42,43,44,45,46,51], task scheduling [9,10,11,33,34], model selection [38], etc.…”

Section: Related Workmentioning

confidence: 99%

Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture

Chen

Fang

Chen

et al. 2019

Int J Parallel Prog

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Sparse matrix-vector multiplications (SpMV) are common in scientific and HPC applications but are hard to be optimized. While the ARMv8based processor IP is emerging as an alternative to the traditional x64 HPC processor design, there is little study on SpMV performance on such new many-cores. To design efficient HPC software and hardware, we need to understand how well SpMV performs. This work develops a quantitative approach to characterize SpMV performance on a recent ARMv8-based many-core architecture, Phytium FT-2000 Plus (FTP). We perform extensive experiments involved over 9,500 distinct profiling runs on 956 sparse datasets and five mainstream sparse matrix storage formats, and compare FTP against the Intel Knights Landing many-core. We experimentally show that picking the optimal sparse matrix storage format and parameters is non-trivial as the correct decision requires expert knowledge of the input matrix and the hardware. We address the problem by proposing a machine learning based model that predicts the best storage format and parameters using input matrix features. The model automatically specializes to the many-core architectures we considered. The experimental results show that our approach achieves on average 93% of the best-available performance without incurring runtime profiling overhead.

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“…In [4], a survey on compiler optimization techniques using machine learning is presented. In [36], sequential analysis is combined with active learning to reduce the training samples. In [5], a statistical methodology is applied to infer the probability distribution of the compiler optimizations.…”

Section: Related Workmentioning

confidence: 99%

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Kelefouras

Djemame

2019

J Supercomput

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The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimizations-transformations, that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g. data reuse); therefore compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be Execution Time (ET), Energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases. Firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general purpose CPUs and for seven well known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand written optimized code and Polly. The exploration space from which the near-optimum parameters are selected, is reduced from 17 up to 30 orders of magnitude. Keywords code optimizations • data cache • register blocking • loop tiling • high performance • energy consumption • data reuse Address(es) of author(s) should be given E(total)

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Minimizing the cost of iterative compilation with active learning

Cited by 39 publications

References 54 publications

Predição de Desempenho com Graph Neural Networks

Predição de Desempenho com Graph Neural Networks

Optimizing Sparse Matrix–Vector Multiplications on an ARMv8-based Many-Core Architecture

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

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