Minimizing peak current via opposite-phase clock tree

Nieh, Yow-Tyng; Huang, Shih-Hsu; Hsu, Sheng-Yu

doi:10.1145/1065579.1065629

Cited by 41 publications

(14 citation statements)

References 9 publications

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“…Bounded skew clock routing algorithms were developed by [27,28,29,30]. Moreover, power optimal clock buffer insertion and temperature aware clock tree optimization techniques were developed in [17] and [18], respectively, while clock buffer polarity assignment techniques were proposed for power noise reduction by [31,32,33,34]. In the 2D clock tree synthesis researches, the DME [22,23,24,25] algorithm constructs a wirelength optimal zero skew clock tree for a given tree topology under the linear delay model, and a suboptimal clock tree under the Elmore delay model [19,20,21].…”

Section: Introductionmentioning

confidence: 99%

Clock tree embedding for 3D ICs

Kim,

Kim

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

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Section: Introductionmentioning

confidence: 99%

Clock tree embedding for 3D ICs

Kim,

Kim

2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…Rahimi [4] shows that peak current can be reduced by spreading out the clock latencies. Nieh et al [3] use an opposite-phase scheme to reduce the peak current caused by the clock tree. Wu et al [6] propose a flip-flop resynthesis technique to reduce the peak current and voltage drop by staggering the switching time of flip-flops using delay cells.…”

Section: Introductionmentioning

confidence: 99%

Peak current reduction by simultaneous state replication and re-encoding

Lin

et al. 2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Peak current is one of the important considerations for circuit design and testing in the deep sub-micron technology. In a synchronous finite state machine (FSM), it is observed that the peak current happens at the moment of state transitions and it has a strong correlation with the maximum number of state registers switching in the same direction simultaneously [2], which we refer to as the peak switching value (PSV). We propose a FSM synthesis method to reduce P SV by seamlessly combining state replication and state re-encoding techniques.Our experiments show that out of 52 FSM benchmarks encoded by a state-of-the-art power-driven encoding algorithm POW3 [1], 36 of them are not optimal in terms of PSV. Our approach can improve on 34 of them with an average 39.2% PSV reduction, while the only comparable PSV-driven FSM synthesis technique [2] can improve on 27 benchmarks with an average 24.5% reduction. Furthermore, we compare our approach with [2] after the FSMs are implemented using an industry EDA tool. The results show that our approach reduces the peak current in the circuits by 13% on average and the total power by 3% with a mere 2% overhead in area.

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“…For example, in Sapatnekar and Su [2003], it shows that 0.1V power noise will incur 79.8% inverter delay variations when the nominal V dd is 0.6V by Berkeley Predictive Technology Model with 45nm technology. 1 To reduce peak current caused by clock tree network, Nieh et al [2005] proposed an opposite-phase approach whose main idea is explained in Figures 1(a) and 1(b). In Figure 1(a), there is a binary clock tree composed of clock buffers.…”

Section: Introductionmentioning

confidence: 99%

“…Although peak current is successfully reduced in Nieh et al [2005], the power/ground noises in a local area are not. Samanta et al [2006] observed that power/ground noises are sensitive to the locations of clock buffers.…”

Section: Introductionmentioning

confidence: 99%

Skew-aware polarity assignment in clock tree

Chen

Hwang

2009

ACM Trans. Des. Autom. Electron. Syst.

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In modern sequential VLSI designs, clock tree plays an important role in synchronizing different components in a chip. To reduce peak current and power/ground noises caused by clock network, assigning different signal polarities to clock buffers is proposed in previous work. Although peak current and power/ground noises are minimized by signal polarities assignment, an assignment without timing information may increase the clock skew significantly. As a result, a timing-aware signal polarities assigning technique is necessary. In this article, we propose a novel signal polarities assigning technique which can not only reduce peak current and power/ground noises simultaneously but also render the clock skew in control. The experimental result shows that the clock skew produced by our algorithm is 94% of original clock skew in average while the clock skews produced by three algorithms (Partition, MST, Matching) in the absence of post clock tuning steps in the previous work are 235%, 272%, and 283%, respectively. Moreover, our algorithm is as efficient as the three algorithms of the previous work in reducing peak current and power/ground noises.

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Minimizing peak current via opposite-phase clock tree

Cited by 41 publications

References 9 publications

Clock tree embedding for 3D ICs

Clock tree embedding for 3D ICs

Peak current reduction by simultaneous state replication and re-encoding

Skew-aware polarity assignment in clock tree

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