Minimizing MLC PCM write energy for free through profiling-based state remapping

Zhao, Mengying; Xue, Yuan; Yang, Chengmo

doi:10.1109/aspdac.2015.7059056

Cited by 25 publications

(5 citation statements)

References 18 publications

(23 reference statements)

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“…The method improves system performance by 19.2%, and memory energy efficiency by 14.4% over the state-of-the-art MLC PCM baseline system, which does not employ bit decoupling. Zhao et al [2015] found that dynamic state remapping (DSR) generates locally optimal remapping decisions without considering the similarity between the new data and the old data stored in the memory. Therefore, when redundant write elimination (RWE) is applied, DSR may not be optimal, since it possibly introduces more transitions and more energy consumption.…”

Section: Mapping and Buffering Data In Mlc Pcmmentioning

confidence: 99%

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Zhang

2016

J. Emerg. Technol. Comput. Syst.

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With dramatic growth of data and rapid enhancement of computing powers, data accesses become the bottleneck restricting overall performance of a computer system. Emerging phase-change memory (PCM) is byte-addressable like DRAM, persistent like hard disks and Flash SSD, and about four orders of magnitude faster than hard disks or Flash SSDs for typical file system I/Os. The maturity of PCM from research to production provides a new opportunity for improving the I/O performance of a system. However, PCM also has some weaknesses, for example, long write latency, limited write endurance, and high active energy. Existing processor cache systems, main memory systems, and online storage systems are unable to leverage the advantages of PCM, and/or to mitigate PCM's drawbacks. The reason behind this incompetence is that they are designed and optimized for SRAM, DRAM memory, and hard drives, respectively, instead of PCM memory. There have been some efforts concentrating on rethinking computer architectures and software systems for PCM. This article presents a detailed survey and review of the areas of computer architecture and software systems that are oriented to PCM devices. First, we identify key technical challenges that need to be addressed before this memory technology can be leveraged, in the form of processor cache, main memory, and online storage, to build high-performance computer systems. Second, we examine various designs of computer architectures and software systems that are PCM aware. Finally, we obtain several helpful observations and propose a few suggestions on how to leverage PCM to optimize the performance of a computer system. ACM Reference Format:Chengwen Wu, Guangyan Zhang, and Keqin Li. 2016. Rethinking computer architectures and software systems for phase-change memory.

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Section: Mapping and Buffering Data In Mlc Pcmmentioning

confidence: 99%

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Zhang

2016

J. Emerg. Technol. Comput. Syst.

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“…(1) while not empty do (2) if there is an V with degree ≤ then (3) delete V (4) else (5) obtain the frequency set by offline profiling (6) sort variables based on the descending write cost (7) choose V with MAX COST (8) add V to spilling list (9) delete V (10) end if (11) if no variable has been spilled then (12) color the variables in reverse order of deleting (13) else (14) spill each V ∈ everywhere (15) rebuild the interference graph and repeat the procedure (16) end if (17) end while Algorithm 2: SSCM-based register allocation algorithm. Thus, all accesses take the same amount of time.…”

Section: Methodsmentioning

confidence: 99%

“…The consumed energy is accumulated by each 2-bit state transition in the register. Each register is 64-bit long and the bits in the same register can be programmed simultaneously [7]. For every register, the overall energy consumption is determined by the product of each state to program and the energy of each state.…”

Section: Dynamic Energymentioning

confidence: 99%

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State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Gong

Chen

et al. 2017

VLSI Design

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Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology to build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAM-based registers, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of hard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency and energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different write state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling priority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost minimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost model is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed cost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show that the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register design.

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“…This property is utilized to respectively represent "0" and "1". Furthermore, with more fine-grained resistance partitions, each cell can represent multiple bits [8,9]. Writing to PCM requires heating the phase change material, which is more time consuming than reading.…”

Section: Pcm Preliminariesmentioning

confidence: 99%

Secure and Durable (SEDURA)

Liu

Yang

2015

Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM

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Phase changing memory (PCM) is considered a promising candidate for next-generation main-memory. Despite its advantages of lower power and high density, PCM faces critical security challenges due to its non-volatility: data are still accessible by the attacker even if the device is detached from a power supply. While encryption has been widely adopted as the solution to protect data, it not only creates additional performance and energy overhead during data encryption/decryption, but also hurts PCM lifetime by introducing more writes to PCM cells.In this paper, we propose a framework that integrates encryption and wear-leveling so as to mitigate the adverse impact of encryption on PCM performance and lifetime. Moreover, by randomizing the address space during wearleveling, an extra level of protection is provided to the data in memory. We propose two algorithms that respectively prioritize data security and memory lifetime, allowing designers to trade-off between these two factors based on their needs. Compared to previous encryption techniques, the proposed SEDURA framework is able to deliver both more randomness to protect data and more balanced PCM writes, thus effectively balancing the three aspects of data security, application performance, and device lifetime.

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Minimizing MLC PCM write energy for free through profiling-based state remapping

Cited by 25 publications

References 18 publications

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

Rethinking Computer Architectures and Software Systems for Phase-Change Memory

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers

Secure and Durable (SEDURA)

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