Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Abstract

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation support for partial reconfigurability includes several key challenges. In particular, reconfiguration algorithms need to be developed to effectively exploit the available area and run-time reconfiguration support for instantiating at run-time the hardware components needed to execute multiple applications concurrently. These new algorithms must be able to achieve maximum application execution performance at a minimum reconfiguration overhead.In this work, we propose a novel design flow that minimizes the amount of core reconfigurations needed to map multiple applications dynamically (i.e., using run-time reconfiguration) on FPGAs. This new mapping flow features a multi-stage design optimization algorithm that makes it possible to reduce the reconfiguration latency up to 43%, by taking into account the reconfiguration costs and SoC block reuse between the different applications that need to be executed dynamically on the FPGA. Moreover, we show that the proposed multi-stage optimization algorithm explores a large set of mapping trade-offs, by taking into account the traffic flows for each application, the run-time reconfiguration costs and the number of reconfigurable regions available on the FPGA.

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

“…The DTM problem can be effectively tackled using the three-stage algorithm that we initially proposed in [6], consisting of: 1) preprocessing; 2) partitioning; and 3) mapping. The three stages are iterated until a feasible solution is found, or until its quality meets certain requirements.…”

“…A linear combination of S, R, and 1 C is then used to select in which slot each core not belonging to is mapped. As shown in [6], it is possible to assign different weights to each metric in order to obtain different tradeoffs between a system in which each application can be deployed after another one with a minimum number of reconfigured regions, and a system in which the communication among the slots is minimal.…”

“…The tuning can be achieved by modifying some of the parameters that affect the selection and the partitioning phases, namely, α and β. Their impact on the algorithm performance has been investigated in [6]. A high value of α-such as 0.4 or higher-leads to a good solution in terms of communication overhead, while a high value of β-such as 0.7 or higher-forces more cores in the base mapping, thus the number of reconfigurations decreases.…”

“…We define a versatile hardware architecture, which divides the reconfigurable area into slots that can be connected using different communication paradigms, such as networks-on-chip (NoCs) [3] or buses. Then, we propose a mapping algorithm for a known set of applications, which we underlined in [6], to optimize both the number of reconfigurations and the communication performance of the system. Finally, we propose a run-time mapper flow that allows the addition of new applications at run-time, by possibly reusing parts of the already-deployed applications, as we first discussed in [7] and [8].…”

Mapeamento e posicionamento de módulos processantes em sistemas dinamicamente reconfiguráveis baseados em redes intrachip.

“…Entre eles pode-se citar (RANA et al, 2009;BERETTA et al, 2010, BERETTA et al, 2011 Apesar destes trabalhos abordarem o problema de mapeamento em SDRs, estes possuem uma abordagem multitarefas, utilizando uma arquitetura específica, que não pode ser aplicadas nas arquiteturas NoC-SDRs complexas apresentadas na seção 2.6.…”