2015
DOI: 10.1016/j.yofte.2014.12.002
|View full text |Cite
|
Sign up to set email alerts
|

MIMO equalization optimized for baud rate clock recovery in coherent 112Gbit/sec DP-QPSK metro systems

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2020
2020
2023
2023

Publication Types

Select...
3

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 13 publications
0
1
0
Order By: Relevance
“…The concept of baud-rate sampling coherent receiver has been demonstrated in several offline-DSP based experiments by introducing an additional low-pass anti-aliasing filter either at the Transmitter side [14] or at the Receiver side [18] to help 1) reduce the impact of sampling phase sensitivity and 2) to increase the CD/PMD tolerance. A 2 × 2 MIMO equalization architecture optimized for baud-rate clock recovery is also reported in [16].…”
Section: Low-power Baud-rate Coherent Dspmentioning
confidence: 99%
“…The concept of baud-rate sampling coherent receiver has been demonstrated in several offline-DSP based experiments by introducing an additional low-pass anti-aliasing filter either at the Transmitter side [14] or at the Receiver side [18] to help 1) reduce the impact of sampling phase sensitivity and 2) to increase the CD/PMD tolerance. A 2 × 2 MIMO equalization architecture optimized for baud-rate clock recovery is also reported in [16].…”
Section: Low-power Baud-rate Coherent Dspmentioning
confidence: 99%