Millimeter-scale integrated and wirewound coils for powering implantable neural microsystems

Feng, Peilong; Constandinou, Timothy G.; Yeon, Pyungwoo; Ghovanloo, Maysam

doi:10.1109/biocas.2017.8325184

Cited by 10 publications

(5 citation statements)

References 17 publications

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“…We refer to them in the rest of this paper as in-CMOS (fully-integrated coils), above-CMOS (post-processed on top of CMOS substrate), and around-CMOS (wirewound around the CMOS chip). This study builds upon our earlier work [14], now extended to three types of coils by adding above-CMOS coils into our comparison. Also, around-CMOS coil has comparable dimensions (4 mm × 4 mm) to the above-CMOS and in-CMOS coils (previously this was 1 mm × 1 mm).…”

Section: Introductionmentioning

confidence: 96%

Chip-Scale Coils for Millimeter-Sized Bio-Implants

Feng

Yeon

Cheng

et al. 2018

IEEE Trans. Biomed. Circuits Syst.

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Next generation implantable neural interfaces are targeting devices with mm-scale form factors that are freely floating and completely wireless. Scalability to more recording (or stimulation) channels will be achieved through distributing multiple devices, instead of the current approach that uses a single centralized implant wired to individual electrodes or arrays. In this way, challenges associated with tethers, micromotion, and reliability of wiring is mitigated. This concept is now being applied to both central and peripheral nervous system interfaces. One key requirement, however, is to maximize specific absorption rate (SAR) constrained achievable wireless power transfer efficiency (PTE) of these inductive links with mm-sized receivers. Chip-scale coil structures for microsystem integration that can provide efficient near-field coupling are investigated. We develop near-optimal geometries for three specific coil structures: in-CMOS, above-CMOS (planar coil post-fabricated on a substrate), and around-CMOS (helical wirewound coil around substrate). We develop analytical and simulation models that have been validated in air and biological tissues by fabrications and experimental measurements. Specifically, we prototype structures that are constrained to a 4 mm 4 mm silicon substrate, i.e., the planar in-/above-CMOS coils have outer diameters 4 mm, whereas the around-CMOS coil has an inner diameter of 4 mm. The in-CMOS and above-CMOS coils have metal film thicknesses of 3- m aluminium and 25- m gold, respectively, whereas the around-CMOS coil is fabricated by winding a 25-m gold bonding wire around the substrate. The measured quality factors (Q) of the mm-scale Rx coils are 10.5 @450.3 MHz (in-CMOS), 24.61 @85 MHz (above-CMOS), and 26.23 @283 MHz (around-CMOS). Also, PTE of 2-coil links based on three types of chip-scale coils is measured in air and tissue environment to demonstrate tissue loss for bio-implants. The SAR-constrained maximum PTE measured (together with resonant frequencies, in tissue) are 1.64% @355.8 MHz (in-CMOS), 2.09% @82.9 MHz (above-CMOS), and 3.05% @318.8 MHz (around-CMOS).

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Section: Introductionmentioning

confidence: 96%

Chip-Scale Coils for Millimeter-Sized Bio-Implants

Feng

Yeon

Cheng

et al. 2018

IEEE Trans. Biomed. Circuits Syst.

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“…This shows the bonding pads, inductive coil, seal ring, and core ENGINI system to scale. See [16], [28] for details on coil fabrication and probe assembly.…”

Section: Measured Resultsmentioning

confidence: 99%

Autonomous SoC for Neural Local Field Potential Recording in mm-Scale Wireless Implants

Leene

Maslik

Feng

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ∆Σ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 µm CMOS technology allowing for waferscale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77µVrms. The resulting electronics has a core area of 2.1 mm 2 and a power budget of 92 µW.

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“…PSCs are characterised by high reliability and ease of manufacturing, in particular with micro-and nano-fabrication processes. However, the quality factor in PSCs is lower than in WWCs [24], [25]. The two geometries are also characterized by different key parameters.…”

Section: A Fundamental Principlesmentioning

confidence: 99%

“…The optimal design of the matching network is an interesting strategy to adjust the phase angle (aiming at θ → 90°). Similar to IPT, the capacitive coupling coefficient k c is obtained from (25):…”

Section: A General Principlesmentioning

confidence: 99%