Migrating Functionality from ROMS to Embedded Multipliers

Morris, Gareth W.; Constantinides, George A.; Cheung, Peter Y. K.

doi:10.1109/fccm.2004.43

Cited by 6 publications

(6 citation statements)

References 2 publications

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“…However, research concerning the exploitation of heterogeneity for a particular application has recently started to appear in the literature. In [8], the authors propose an approach for exchanging embedded RAMs for multipliers, whereas in [9] the authors propose an algorithm that identifies part of the circuit that can be implemented in embedded RAMs.…”

Section: Introductionmentioning

confidence: 99%

A Novel 2D Filter Design Methodology

Bouganis

Constantinides

Cheung

2005 IEEE International Symposium on Circuits and Systems

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Abstract-In many image processing applications, fast convolution of an image with a large 2D filter is required. Field Programable Gate Arrays (FPGAs) are often used to achieve this goal due to their fine grain parallelism and reconfigurability. However, the heterogeneous nature of modern reconfigurable devices is not usually considered during design optimization. This paper proposes an algorithm that explores the implementation architecture of 2D filters, targeting the minimization of the required area, by optimizing the usage of the different components in the heterogenous device. Experiments show that the proposed algorithm can achieve on average 55% reduction in the required area when compared to current techniques.

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Section: Introductionmentioning

confidence: 99%

A Novel 2D Filter Design Methodology

Bouganis

Constantinides

Cheung

2005 IEEE International Symposium on Circuits and Systems

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“…Overviewed are techniques for ROM to arithmetic conversion using modified polynomial approximation. The work described here expands on [3] and uses the transformation as a basis for providing a resource constrained guided synthesis system.…”

Section: Introductionmentioning

confidence: 99%

“…Application of polynomial approximation to the problem of emulating ROM functionality with arithmetic operations was the subject of a previous paper by the authors [3]. Overviewed are techniques for ROM to arithmetic conversion using modified polynomial approximation.…”

Section: Introductionmentioning

confidence: 99%

Using DSP blocks for ROM replacement: a novel synthesis flow

Morris

Constantimdes

Cheung

International Conference on Field Programmable Logic and Applications, 2005.

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This paper describes a method based on polynomial approximation for transferring ROM resources used in FPGA designs to multiplication and addition operations. The technique can be applied to any FPGA architecture containing embedded multiplication, however this paper focuses on using the DSP blocks of Altera Stratix and Stratix II architectures. The transformation is combined with other resource transfers and integrated in a synthesis flow targeting designs implemented on heterogeneous FPGAs. The main advantage of such a system is in handling user constraints on each type of resource: DSP block, LUT and ROM, in addition to timing-related constraints. The flow is based on an extension to the Altera Quartus II synthesis software and Quartus University Interface Program (QUIP) framework. Results are provided for implementations of benchmark algorithms and it is shown through a design-space exploration that the set of achievable designs for the algorithms has been extended by the use of the proposed methods.

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“…However, research concerning the exploitation of heterogeneity for a particular application has recently started to appear in the literature. In [9], the authors propose an approach for exchanging embedded RAMs for multipliers, whereas in [14] the author proposes an algorithm that identifies part of the circuit that can be implemented in embedded RAMs.…”

Section: Introductionmentioning

confidence: 99%