Microstructure investigation of TSV copper film

Abstract

Copper Through-Silicon Via (Cu TSV) is becoming a key technology for three dimensional (3D) packaging and 3D integrated circuit (IC) applications. The microstructure of the Cu TSV is important as it not only affects the electrical properties, but may play a role in its reliability such as protrusion. In this study, physical vapor deposition (PVD) and electroplated (ECP) Cu TSV microstructure evolution with Ti and Ta barrier after thermal annealing was investigated. As deposited PVD Cu grain showed a preferred orientation on (111) and transformed into (001) after annealing. On the other hand, ECP Cu grain orientation appears to be random for both samples before and after annealing. The grain size for both PVD and ECP increased substantially after annealing at 410°C 30 min because of grain growth. However, the grain growth was more significant in Ti-barrier Cu TSV sample than the Ta-barrier one.

3D EBSD characterizations on copper TSV for 3D interconnections

“…It is known that in copper, there are normal grain boundaries and twin grain boundaries. These two types of grain boundaries were also observed in TSV [7]. Grain boundary type information in TSV is important as they may affect the resistivity of TSV itself [11,12].…”

Electrodeposition and Growth Mechanism of Nanotwinned Copper in High Aspect-Ratio via Structures

“…A tremendous research effort has been dedicated to the fabrication, characterization and process integration of Cu wires in microelectronic devices. 3 Besides mechanical and electrical merits, dense nanoscale Σ3 coherent twin boundaries (CTBs) also improve electromigration resistance, 4 thermal stability, 5 and corrosion/oxidation resistance of Cu metallization. 6 Although electrodeposition is a mature process for filling high-AR via structures in semiconductor process technology, introducing nanoscale CTBs into extremely small-sized interconnects has never been an easy task.…”