Microstrip Impedance Management through Multilayer PCB Stack-Up: Discontinuity Compensation Voids with Asymmetric Dielectrics

Abstract

To process high-frequency signals on a printed circuit board (PCB), it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0. Modern PCBs are complex multilayer designs, utilizing either only high-end laminates, low-end laminates, or a combination of both. The on-board component footprints usually have larger pads that become discontinuities and corrupt the impedance of critical traces. One way to address this issue is to include reference plane cutouts as a measure of compensation. This paper aims to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts. The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs that strictly comprise high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice. S-parameter measurements are performed and confirmed by time domain reflectometry (TDR) measurements.

Applying Characteristic Impedance Compensation Cut-Outs to Full Radio Frequency Chains in Multi-Layer Printed Circuit Board Designs

“…This has been reported in various papers and design notes [ 8 , 9 , 10 , 11 , 12 ], but they are only single case studies addressing passive surface-mount device components such as 0201 or 0402 package size capacitors. Moreover, impedance compensation techniques, including reference plane cut-out introduction, have been thoroughly analyzed and improvements have been proposed in previous papers [ 13 , 14 ] on the latter topic.…”

“…Thus, the third copper layer becomes the reference layer for these pads. Different stack-ups have been thoroughly analyzed in [ 14 ], while obtaining the optimal size of the cutout has been discussed in [ 13 ].…”

A Method of Optimizing Characteristic Impedance Compensation Using Cut-Outs in High-Density PCB Designs

“…As mentioned in our earlier literature reviews [ 11 , 12 ], the most common design strategy is to make a cut-out the same width as the discontinuity, although such a window may be too small to minimize capacitance as much as possible. This is very clearly shown in Figure 1 b, where the structure contains two dielectrics and three metal layers.…”

“…The reference plane cut-out compensation technique, also sometimes referred to as compensation using a defected ground structure (DGS), has been a topic of research in multiple papers that cover different case–studies, such as SMA connector pads, track bends, etc., [ 9 , 10 , 11 , 12 ]. The main principle behind reference plane cut-out compensation is altering the per-length-capacitance and per-length-inductance of a discontinuity in a controlled impedance scenario by varying the depth of the reference (ground) plane in a multi-layer PCB.…”

“…Despite the fact that reference plane cut-outs help to mitigate the difference between track and pad impedances, the shift in impedance with each introduced cut-out is discrete and the step size depends on the number of available electrical layers, the thickness of each laminate, and the properties of the dielectric material. In some cases, a single reference plane cut-out is not enough to achieve the target impedance, but a successive cut-out on the next reference plane overshoots the result [ 11 ]. Therefore, the discontinuity impedance after the first compensation step is closer to Z 0 than that without, but is still not enough, and the application of a second cut-out might even worsen the achieved result.…”