Microprocessor-based System Test using Debug Interface

Devadze, Sergei; Jutman, Artur; Tsertov, Anton; Instenberg, Martin; Ubar, Raimund

doi:10.1109/norchp.2008.4738291

Cited by 3 publications

(6 citation statements)

References 10 publications

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“…The test program may be designed accordingly to on-line or off-line testing [11] principles. In on-line mode, the test patterns are fed through the debug port during the execution of test program while for the off-line case test program already contains embedded test patterns for the selected UUT.…”

Section: A Test Applicationmentioning

confidence: 99%

“…The on-line mode is also beneficial when dealing with devices with a small internal memory. See [11] for more details.…”

Section: A Test Applicationmentioning

confidence: 99%

“…The test project encloses the test program(s) either with built in test vectors or test vectors in a standalone file (off-line or on-line testing [11]). Test project may also include microcode programs for test procedure acceleration (e.g.…”

Section: B Test Automationmentioning

confidence: 99%

See 2 more Smart Citations

SoC and Board Modeling for Processor-Centric Board Testing

Tsertov

Ubar

Jutman³

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Many contemporary electronic systems are based on System-on-Chips (SoC) such as micro-controllers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that the restricted capabilities of BS with respect of such modern challenges as dynamic (timing-accurate), at-speed and high-speed testing as well as in-system programming create considerable troubles for test engineers in production environments. In this paper, we point out particular challenges in testing the system's infrastructure beyond the SoCs as well as propose a general modeling methodology for test automation for microprocessor SoC-based system boards. The new so-called "Lego-style" test automation methodology forms a complimentary solution to traditional boundary scan. Together, they provide extended fault coverage that targets shorts, opens, stuck-at faults as well as dynamic faults (e.g. delays and transition faults). The "Legostyle" model allows reducing the labour effort drastically once the library of model components is created.

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Section: A Test Applicationmentioning

confidence: 99%

“…The on-line mode is also beneficial when dealing with devices with a small internal memory. See [11] for more details.…”

Section: A Test Applicationmentioning

confidence: 99%

See 1 more Smart Citation

SoC and Board Modeling for Processor-Centric Board Testing

Tsertov

Ubar

Jutman³

et al. 2011

2011 14th Euromicro Conference on Digital System Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…The test program may be designed accordingly to on-line or offline testing [10] principles. In on-line mode, the test patterns are fed through the debug port during the execution of test program while for the off-line case test program already contains embedded test patterns for the selected UUT.…”

Section: Test Applicationmentioning

confidence: 99%

“…The online mode is also beneficial when dealing with devices with a small internal memory. See [10] for more details.…”

Section: Test Applicationmentioning

confidence: 99%

Testing beyond the SoCs in a lego style

Tsertov

Jutman

Devadze³

2010

2010 East-West Design &Amp; Test Symposium (EWDTS)

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many contemporary electronic systems are based on such System-on-Chips (SoC) as microcontrollers or signal processors that communicate with many peripheral devices on the system board and beyond. While, SoC test was a topic of extremely high interest during the last decade, the test beyond SoCs didn't get much attention after introduction of Boundary Scan (BS) 30 years ago. It is not a surprise that the restricted capabilities of BS with respect of such modern challenges as dynamic (timing-accurate), at-speed and high-speed testing as well as in-system programming create considerable troubles for test engineers in production environments. In this paper, we point out particular challenges in testing the system's infrastructure beyond the SoCs as well as propose a general modeling methodology for test automation for microprocessor SoC-based system boards. The new so-called "lego-style" test automation methodology forms a complimentary solution to traditional boundary scan. Together, they provide extended fault coverage that targets shorts, opens, stuck-at faults as well as dynamic faults (e.g. delays and transition faults). The "legostyle" model allows reducing the labor effort drastically once the library of model components is created.

show abstract