MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms

Abstract

While most research papers on computer architectures include some performance measurements, these performance numbers tend to be distrusted. Up to the point that, after so many research articles on data cache architectures, for instance, few researchers have a clear view of what are the best data cache mechanisms. To illustrate the usefulness of a fair quantitative comparison, we have picked a target architecture component for which lots of optimizations have been proposed (data caches), and we have implemented most of the hardware data cache optimizations of the past 4 years in top conferences. Then we have ranked the different mechanisms, or more precisely, we have examined the impact of benchmark selection, process model precision,. . . on ranking, and obtained some surprising results. This study is part of a broader effort, called MicroLib, aimed at promoting the disclosure and sharing of simulator models.

When Prefetching Works, When It Doesn’t, and Why

“…For different prefetch mechanisms, please refer to Vanderwiel and Lilja [2000] and the paper on MicroLib [Perez et al 2004]. In this section, we only discuss the most relevant work that focuses on the limitations of software prefetching and the interaction of hardware and software prefetching.…”

“…Although others have studied the benefits and limitations of hardware and software prefetching [Emma et al 2005;Perez et al 2004;Vanderwiel and Lilja 2000], we are not aware of any study that explains why some benchmarks show positive/neutral/negative interactions from combined software and hardware prefetching with concrete examples from real benchmarks. We seek to provide such insights in this article by analyzing the source code, data structures, and algorithms used in applications.…”

“…Although a variety of software and hardware prefetching mechanisms for tolerating cache miss latency exist [Callahan et al 1991;Perez et al 2004;Vanderwiel and Lilja 2000], only relatively simple software prefetching algorithms have appeared in state-of-the-art compilers like icc [ICC] and gcc . Therefore, performanceaware programmers often have to insert prefetching intrinsics manually [Intel 2011].…”

Temporal Streaming of Shared Memory

“…We also compare against the Global History Buffer (GHB) prefetcher proposed by Nesbit and Smith [25]. GHB was recently shown to outperform a wide variety of other prefetching mechanisms on SPEC applications [26]. In GHB, consumption misses are recorded in an on-chip circular buffer similar to the CMOB, and are located using an onchip fully-associative index table.…”

“…Prefetching [26] or forwarding [17] techniques seek to hide the entire cache (read) miss latency. These techniques have been shown to be effective for workloads with regular (e.g., strided) memory access patterns.…”