Microarchitectural techniques for power gating of execution units

Abstract

Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for power gating execution units is then evaluated, for the range of relevant break-even points determined by the analytical equations, using a state-of-the-art out-of-order superscalar processor model. The power gating potential of the floating-point and fixed-point units of this processor is then evaluated using three different techniques to detect opportunities for entering sleep mode; ideal, time-based, and branch-misprediction-guided. Our results show that using the time-based approach, floating-point units can be put to sleep for up to 28% of the execution cycles at a performance loss of 2%. For the more difficult to power-gate fixed-point units, the branch misprediction guided technique allows the fixed-point units to be put to sleep for up to 40% more of the execution cycles compared to the simpler time-based technique, with similar performance impact. Overall, our experiments demonstrate that architectural techniques can be used effectively in power-gating execution units.

Segmented Buffer for NOC Router

“…Previous works have been done for this purpose. Among them, DVFS method [4], [5], power gating techniques [6]- [9]. Power gating is mainly of two types: coarse-grained and fine-grained.…”

Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment

“…As leakage is becoming a growing concern in the current microprocessor designs, several leakage control mechanisms have been studied [9][11] [19] [20]. All these mechanisms try to reduce leakage when the circuit is in idle state.…”

“…All these mechanisms try to reduce leakage when the circuit is in idle state. Power gating [9] consists of shutting down parts of the circuit by cutting their power supply by means of high threshold header or footer transistors. SSGC [11] is similar to power gating as this technique also cuts the power supply to the circuit.…”

“…Many leakage control techniques have been studied [9][11] [19] [20], power gating being one of the most prominent ones. Power gating cuts the supply voltage to the idle functional units, resulting in leakage energy savings.…”

Implementation of WSN node Using Hardware Specialization

“…Since the static power contribution will necessarily grow due to the possibly numerous number of hardware tasks implemented on chip, we propose to combine our approach with power gating techniques [5]. The idea consists in supplying power to the hardware controller only when its associated task is to be executed.…”