Micro-architecture Performance Estimation by Formula

Abstract

Abstract. An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design options including memory hierarchy, branch prediction, issue width and changes in pipeline depth at all pipeline stages. The model requires a minimal number of cycle accurate and trace driven simulations to calibrate and once calibrated estimates performance by formula. The model estimates the performance of arbitrary micro-architecture configurations with an average error of 6.4%. During early design stages when cycle accurate simulation is prohibitive an analytical model can provide guidance to designers to increase design quality and reduce design effort. This allows the design of an embedded processor to be rapidly tuned to its application by reducing the cost of exploring the design space.

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

“…6 assumes that ETV i for each array i is additive when computing the overall ETV . It is known from previous work [30,14] that, the penalty of different units can overlap, thus, how can this additive claim be accurate?…”

“…The simple summation of ETV i s is found to be accurate for the benchmarks, faulty arrays, and microarchitecture used in this study. If more accuracy is needed, future work can consider the detail interaction between units [30,14]. 3 The model used in this section to estimate M i is from [27] and is presented here for completeness.…”