MiBench: A free, commercially representative embedded benchmark suite

Guthaus, Matthew R.; Ringenberg, Jeffrey; Ernst, Daniel; Austin, Todd; Mudge, Trevor; Brown, Richard B.

doi:10.1109/wwc.2001.990739

Cited by 1,926 publications

(1,406 citation statements)

References 5 publications

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“…The telecom and consumer suite of the MiBench benchmark [18] provides representative applications for these devices. They are used to evaluate memory and performance overhead.…”

Section: Discussionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient and Effective Buffer Overflow Protection on ARM Processors

Strackx

Younan

Philippaerts

et al. 2010

Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices

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Abstract. Although many countermeasures have been developed for desktop and server environments, buffer overflows still pose a big threat. The same approach can be used to target mobile devices. Unfortunately, they place more severe limitations on countermeasures. Not only are the performance requirements at least as important, memory and power consumption need to be considered as well. Moreover, processors used in mobile devices generally are equipped with a different instruction set. Therefore countermeasures may not be ported easily. Multistack is an effective countermeasure against stack-based buffer overflows. It protects applications by using multiple stacks to separate possible attack targets from possible sources. However, its performance overhead will no longer be negligible on the ARMv7 platform (widely used on mobile devices) and it wastes too much memory, making it too costly for mobile applications. We propose 3 methods to reduce memory overhead up to 28% with only a 3.91% performance overhead.

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“…The telecom and consumer suite of the MiBench benchmark [18] provides representative applications for these devices. They are used to evaluate memory and performance overhead.…”

Section: Discussionmentioning

confidence: 99%

“…To evaluate the performance of the different Multistack implementations, we ran the telecom and consumer suite of the MiBench benchmark [18] on a Sharp PC-z1 running Ubuntu Linux 9.04 (kernel 2.6.28). This netbook is equipped with an ARM Cortex-A8 CPU running at 800 MHz and 512 MiB RAM.…”

Section: Performance Evaluationmentioning

confidence: 99%

Efficient and Effective Buffer Overflow Protection on ARM Processors

Strackx

Younan

Philippaerts

et al. 2010

Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices

View full text Add to dashboard Cite

show abstract

“…Each experiment runs for 2 × 10 7 instructions per core with a different benchmark mix randomly selected from our representative pool of benchmark suites. We used WCET benchmarks from Mälardalen University [7], SPLASH2 [29] from the University of Delaware, and MiBench [8] to cover a broad range of applications, with a mix of integer, floating-point and memory instructions. For each experiment different duty-cycle levels are set for each topological ring in the architecture.…”

Section: A Experimental Setup and Methodology Evaluationmentioning

confidence: 99%

Thermal/performance trade-off in network-on-chip architectures

Zoni

Corbetta

Fornaciari

2012

2012 International Symposium on System on Chip (SoC)

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Abstract-Multi-core architectures are a promising paradigm to exploit the huge integration density reached by highperformance systems. Indeed, integration density and technology scaling are causing undesirable operating temperatures, having net impact on reduced reliability and increased cooling costs. Dynamic Thermal Management (DTM) approaches have been proposed in literature to control temperature profile at run-time, while design-time approaches generally provide floorplan-driven solutions to cope with temperature constraints. Nevertheless, a suitable approach to collect performance, thermal and reliability metrics has not been proposed, yet. This work presents a novel methodology to jointly optimize temperature/performance trade-off in reliable high-performance parallel architectures with security constraints achieved by workload physical isolation on each core. The proposed methodology is based on a linear formal model relating temperature and duty-cycle on one side, and performance and duty-cycle on the other side. Extensive experimental results on real-world use-case scenarios show the goodness of the proposed model, suitable for design-time system-wide optimization to be used in conjunction with DTM techniques.

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“…1 shows the contention level as well as the dynamic power for router five considering a 16-core 2D-mesh where the NoC runs at 100 MHz (blue lines) and 1 GHz (red lines). In both scenarios the cores run at 1 GHz, executing the qsort benchmark taken from the MiBench suite [16]. It is obvious that the contention is lowered when the NoC operates at the higher frequency, a benefit paid in terms of time and power.…”

Section: Motivational Examplementioning

confidence: 99%

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

Zoni

Terraneo

Fornaciari

2015

Journal of Systems Architecture

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a b s t r a c tNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi-and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ⁄ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting.

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MiBench: A free, commercially representative embedded benchmark suite

Cited by 1,926 publications

References 5 publications

Efficient and Effective Buffer Overflow Protection on ARM Processors

Efficient and Effective Buffer Overflow Protection on ARM Processors

Thermal/performance trade-off in network-on-chip architectures

A control-based methodology for power-performance optimization in NoCs exploiting DVFS

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