Metrics and Measurement Tools in OpenFlow and the OFELIA Testbed

Körner, Marc; Almus, Herbert; Woesner, Hagen; Jungel, Tobias

doi:10.1007/978-3-642-41296-7_8

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…On the LBs side, being most of the required functionalities relatively simple to implement, an hardware based approach may help in scaling performance. Furthermore, layer 2 software based forwarding performance are often surprisingly unsatisfactory [20]. Finally, the presented hardware solution based on a FPGA permits to extend the open-source approach to the hardware domain [2], without incurring in the classical drawbacks of custom hardware development, such as high cost, lack of reprogrammability and flexibility.…”

Section: Introductionmentioning

confidence: 99%

A Load Balancer for a Multi-Stage Router Architecture

Atalla¹,

Bianco²,

Birke³

et al. 2014

IJCA

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Multi-stage software router architectures permit to overcome several limitations inherent to single stage software routers. One of the key elements of the multi-stage architecture under study are the load balancers, which are used to distribute the load among backend routers. However, using a PC (Personal Computer) as a load balancer could create a performance bottleneck in the overall architecture. Since the operations performed by the load balancer are simple, we explore the possibility of an hardware-based implementation of load balancing functionality with the goal of improving its performance. In this paper, we describe the architecture of an FPGA-based load balancer and we present some performance results of its prototype implementation.

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Section: Introductionmentioning

confidence: 99%